Thin-film large-area classifier

A classifier system implementing a deep neural network (DNN), the classifier

• system comprising:
• a weight block;
• a classification block;
• a row selector;
• and
• a sensor array operatively coupled with the weight block, the classification block and the row selector, the sensor array comprising a plurality of sensor cells corresponding to respective neurons in an input layer of the DNN, the plurality of sensor cells arranged in a two-dimensional matrix configuration, row lines, column lines, a data integration line and an integration start line;
• wherein the classifier system is configured such that the plurality of sensor cells share a common terminal connected to the data integration line, the row lines are controlled by the row selector,
• and the column lines receive respective weight values from the weight block, the weight values received from the weight block corresponding to connection weights in the DNN,
• wherein the classification block includes a first integrator receiving a signal generated on the data integration line when the integration start line is selected, and a first thresholding unit receiving a signal from the first integrator, the first thresholding unit operatively coupled to an array of second integrators and second thresholding units arranged in a two-dimensional matrix configuration, the array of second integrators and second thresholding units including row lines, controlled by the row selector, and column lines receiving respective weight values from the weight block, and
• wherein the sensor array comprises a plurality of storage capacitors, a first plurality of select transistors and a second plurality of select transistors, and wherein a gate terminal of each of the first plurality of select transistors in each row is controlled by a corresponding one of the row lines connected to the row selector, a first source/drain terminal of each of the first plurality of select transistors in each column receives a weight value from a corresponding one of the column lines connected to the weight block, a second source/drain terminal of each of the first plurality of select transistors is connected to a corresponding one of the storage capacitors and to a first source/drain terminal of each of the second plurality of select transistors, a gate terminal of each of the second plurality of select transistors is connected to the integration start line, a second source/drain terminal of each of the second plurality of select transistors is connected to a first terminal of each of a corresponding one of the plurality of sensor cells, and a second terminal of each of the plurality of sensor cells is connected to the data integration line.