On-chip memory block circuit
AssigneeXilinx, Inc.
InventorsAhmad R. Ansari, Sagheer Ahmad
Life of this patent
Estimating the term…
Abstract
A memory block circuit can include a plurality of data interfaces, a switch connected to each data interface of the plurality of data interfaces, and a plurality of memory banks each coupled to the switch. Each memory bank can include a memory controller and a random access memory connected to the memory controller. The memory block circuit also includes a control interface and a management controller connected to the control interface and each memory bank of the plurality of memory banks. Each memory bank can be independently controlled by the management controller.
Claims20
A memory block circuit, comprising:
- a plurality of data interfaces;
- a switch connected to each data interface of the plurality of data interfaces;
- a plurality of memory banks each coupled to the switch, wherein each memory bank includes a memory controller and a random access memory connected to the memory controller;
- a control interface;
- a management controller connected to the control interface and each memory bank of the plurality of memory banks, wherein each memory bank is independently controllable by the management controller;
- and
- wherein each memory controller is connected to the switch by a memory protection unit configured to selectively grant access to the memory controller based on an identity of a circuit requesting access and an address range to be accessed.
A device, comprising:
- a processor system including a core configured to execute program code;
- a programmable logic configurable to implement different user-specified circuits;
- a memory block circuit directly connected to the processor system and the programmable logic, wherein the programmable logic and the processor system are configured to access the memory block circuit concurrently;
- and
- wherein the memory block circuit includes a plurality of data interfaces wherein a first data interface of the plurality of data interfaces is connected to the processor system and a second data interface of the plurality of data interfaces is connected to the programmable logic.
A memory block circuit, comprising:
- a plurality of data interfaces;
- a switch connected to each data interface of the plurality of data interfaces;
- a plurality of memory banks each coupled to the switch, wherein each memory bank includes a memory controller and a random access memory connected to the memory controller;
- a control interface;
- a management controller connected to the control interface and each memory bank of the plurality of memory banks, wherein each memory bank is independently controllable by the management controller;
- and
- wherein the control interface, the plurality of data interfaces, the switch, the plurality of memory banks, and the management controller operate at a first clock rate that is a multiple of a second clock rate of a programmable logic connected to at least one of the plurality of data interfaces.
Dependencies are inferred from the claim text.