# US 11,177,123 B2 · Compound semiconductor laminate substrate, method for manufacturing same, and semiconductor element > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,177,123 B2 - Document ID: US11177123B2 - Status: Granted - Kind: B2 - Application number: 16/484,285 - Filed: 2018-02-15 - Published: 2020-01-02 - Granted: 2021-11-16 - Earliest claimed: 2017-02-16 - Assignees: Shin-Etsu Chemical Co., Ltd.; Cusic Inc. - Applicants: Shin-Etsu Chemical Co., Ltd.; Cusic Inc. - Inventors: Hiroyuki Nagasawa; Yoshihiro Kubota; Shoji Akiyama - Web page: https://patentgrep.com/patent/US11177123B2 ## CPC - H10P 10/128: {by direct semiconductor to semiconductor bonding} - H10P 90/12: {Preparing bulk and homogeneous wafers} - H10D 62/405: {Orientations of crystalline planes} - H10P 90/00: Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement - H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass - H10D 62/8325: {Silicon carbide} - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A compound semiconductor laminate substrate comprising two single-crystalline compound semiconductor substrates directly bonded together and laminated, the single-crystalline compound semiconductor substrates having the same composition including A and B as constituent elements and having the same atomic arrangement, characterized in that the front and back surfaces of the laminate substrate are polar faces comprising the same kind of atoms of A or B, and that a laminate interface comprises a bond of atoms of either B or A and is a unipolar anti-phase region boundary plane in which the crystal lattices of the atoms are matched. In this way, the polar faces of the front and rear surfaces of the compound semiconductor laminate substrate are made monopolar, thereby facilitating semiconductor element process designing, and making it possible to manufacture a low-cost, high-performance, and stable semiconductor element without implementing complex substrate processing. ## Claims ### Claim 1 A compound semiconductor laminated substrate comprising: two single-crystalline compound semiconductor substrates each containing A and B as constituent elements and both having the same composition and the same atomic arrangement, which substrates are directly bonded together and laminated, wherein the crystal orientation of the bonded two single-crystalline compound semiconductor substrates are aligned, a front surface and a back surface of the laminated substrate are polar faces made of atoms of the same kind of A or B, and a laminated interface is a unipolar antiphase boundary having bonds of either atoms of B bonded to each other or atoms of A bonded to each other, and at the laminated interface, the two single-crystalline compound semiconductors in the laminated substrate having coherent crystal lattices. ### Claim 2 (depends on 1) The compound semiconductor laminated substrate according to claim 1, which is made of silicon carbide, gallium nitride, gallium arsenic, gallium phosphorus, indium phosphorus, aluminum nitride, or indium antimony. ### Claim 3 (depends on 1) The compound semiconductor laminated substrate according to claim 1, wherein each of the laminated compound semiconductor substrates has a uniform thickness. ### Claim 4 (depends on 1) The compound semiconductor laminated substrate according to claim 1, wherein one of the two compound semiconductor substrates is a thin film of a compound semiconductor. ### Claim 5 (depends on 4) The compound semiconductor laminated substrate according to claim 4, wherein one of the two compound semiconductor substrates is an epitaxial film. ### Claim 6 (depends on 1) A power semiconductor device comprising the compound semiconductor laminated substrate according to claim 1. ### Claim 7 (depends on 1) The compound semiconductor laminated substrate according to claim 1, wherein the crystal lattice of one of the two single-crystalline compound semiconductor substrates and the crystal lattice of the other substrate are continuously connected together of the entire laminated interface. ### Claim 8 (depends on 1) The compound semiconductor laminated substrate according to claim 1, wherein the laminated interface has only bonds of atoms of the same kind of element. ### Claim 9 (depends on 1) The compound semiconductor laminated substrate according to claim 1, wherein the laminated interface essentially consists of the unipolar antiphase boundary having either one of anion-anion bonds or cation-cation bonds. ### Claim 10 (depends on 1) The compound semiconductor laminated substrate according to claim 1, wherein the laminated interface inhibits the motion of dislocations. ### Claim 11 (depends on 1) The compound semiconductor laminated substrate according to claim 1, wherein the unipolar antiphase boundary does not make a semi-metallic behavior. ### Claim 12 (depends on 1) The compound semiconductor laminated substrate according to claim 1, wherein the tolerance between the crystal orientations of the bonded two single-crystalline compound semiconductor substrates is less than or equal to 50 arcsec. ### Claim 13 (depends on 1) The compound semiconductor laminated substrate according to claim 1, wherein the laminated interface is the unipolar antiphase boundary that is parallel to the front and back surfaces of the laminated substrate. ### Claim 14 (depends on 1) The compound semiconductor laminated substrate according to claim 1, wherein the density of incoherent interfaces is less than or equal to 0.1% of the density of atoms constituting the interface at the entire laminated interface. ### Claim 15 (depends on 1) The compound semiconductor laminated substrate according to claim 1, wherein the thickness of each of the two single-crystalline compound semiconductor substrates is in the range of 100 nm to 1,000 μm. ### Claim 16 (depends on 1) The compound semiconductor laminated substrate according to claim 1, further comprising a homoepitaxial layer on at least either of the front and back surfaces of the laminated substrate.