Techniques for reliable clock speed change and associated circuits and methods

A voltage generator, comprising:

• a charge pump circuit coupled to a power supply having a first voltage, and configured to generate a second voltage different than the first voltage based, at least in part, on receiving an output of an oscillator coupled to the charge pump circuit, wherein:
• the oscillator includes:
• a gating flip-flop configured to generate a first signal synchronized with an input clock signal based, at least in part, on receiving the input clock signal, a second signal, and a third signal;
• a first combinational logic configured to receive an inverted third signal and the first signal from the gating flip-flop, and to generate a reset signal that is synchronized with an enable signal for the oscillator;
• a first clock path coupled to the first combinational logic, the first clock path including a first quantity of flip-flops, and configured to receive the input clock signal and the reset signal;
• a second clock path coupled to the first combinational logic, the second clock path including a second quantity of flip-flops, and configured to receive the input clock signal and an inverted reset signal;
• and
• a second combinational logic coupled to the first and second clock paths, the second combinational logic configured to generate the output of the oscillator if the enable signal is active.

A method, comprising:

• generating a first reset signal having at least two logic states;
• generating a second reset signal corresponding to the first reset signal delayed in time such that the second reset signal is synchronized with an input clock signal;
• providing an inverted second reset signal to two or more individual flip-flops of a first clock path, wherein a first flip-flop of the first clock path is configured to receive the input clock signal;
• and
• providing the second reset signal to one or more individual flip-flops of a second clock path, wherein a first flip-flop of the second clock path is configured to receive the input clock signal.