Realization of neural networks with ternary inputs and binary weights in NAND memory arrays

An apparatus, comprising:

• a source line;
• a first bit line;
• a plurality of first word lines;
• a first NAND string connected between the source line and the first bit line, the first NAND string including a first plurality of non-volatile memory cells each connected to a corresponding one of a first plurality of the first word lines;
• a first sense amplifier connected to the first bit line and configured to determine a conductivity state of the first NAND string in response to a set of voltage levels applied concurrently to the first plurality of the first word lines;
• a logic circuit connected to the first plurality of the first word lines;
• and
• a first counter circuit connected to the first sense amplifier and to the logic circuit, the first counter circuit configured to increment a first count in response to the conductivity state determined by the first sense amplifier and to alter the incrementing of the first count in response to an output from the logic circuit indicating a first pattern of voltage levels applied to the first plurality of the first word lines.

A method, comprising:

• receiving one or more first input values;
• translating each of the one or more first input values into a corresponding a first voltage pattern, each first voltage pattern being one of a plurality of voltage patterns comprising a set of N voltage values;
• applying the one or more first voltage patterns to one or more NAND strings connected to a shared bit line, wherein no more than one of the first voltage patterns is applied to any single one of the NAND strings at a time and the set of N voltage values of each of the first voltage patterns are applied to a corresponding N memory cells of a NAND string to which the first voltage pattern is applied;
• determining a number of the one or more NAND strings connected to the shared bit line that conduct in response to the one or more first voltage patterns being applied thereto;
• determining a number of the one or more first voltage patterns that match a predetermined one of the plurality of patterns;
• incrementing a first count based on the number of the one more NAND strings connected to the shared bit line that conduct in response to the one or more first voltage patterns being applied thereto;
• and
• adjusting the first count based on the number of the one or more first voltage patterns that match a predetermined one of the plurality of patterns.