Data transmission code and interface

A data receiving interface for use in a second integrated circuit (IC) for receiving and decoding a data packet sent from a first IC to the second IC via a data bus having four data wires, the data receiving interface arranged to receive four time-dependent binary signals which jointly encode the data packet in signal edges thereof, each of the signals being associated with a unique wire of the data bus and spanning a temporal cycle T within which are defined four consecutive time stamps T1 . . . T4 at which edges can occur in the signals, the data receiving interface further arranged to decode the data packet from the four signals, wherein:

• irrespective of a data packet content, at each time stamp T1 . . . T4 at least one of the four signals has an edge to enable clock recovery at the data receiving interface;
• a time difference between T2 and T3 is greater than both a time difference between T1 and T2 and also a time difference between T3 and T4;
• and
• no signal has edges at both T1 and T2 and no signal has edges at both T3 and T4.

A method of encoding and sending a data packet from a first integrated circuit (IC) to a second IC via a data bus having four data wires, the method comprising:

• generating, at a data transmission interface of the first IC, four time-dependent binary signals which jointly encode the data packet in signal edges thereof, each of the signals being associated with a unique wire of the data bus and spanning a cycle T within which are defined four consecutive time stamps T1 . . . T4 at which edges can occur in the signals;
• and
• transmitting the signals to the second IC substantially in parallel on their respective bus wires, wherein:
• irrespective of a data packet content, at each time stamp T1 . . . T4 at least one of the four signals has an edge to enable clock recovery at the second IC;
• a time difference between T2 and T3 is greater than both a time difference between T1 and T2 and also a time difference between T3 and T4;
• and
• no signal has edges at both T1 and T2 and no signal has edges at both T3 and T4.

A method of receiving and decoding a data packet sent from a first integrated circuit, IC, to a second IC via a data bus having four data wires, the method comprising:

• receiving, at a data receiving interface of the second IC, four time-dependent binary signals which jointly encode the data packet in signal edges thereof, each of the signals being associated with a unique wire of the data bus and spanning a cycle T within which are defined four consecutive time stamps T1 . . . T4 at which edges can occur in the signals;
• and
• decoding the data packet from the four signals at the data receiving interface, wherein:
• irrespective of a data packet content, at each time stamp T1 . . . T4 at least one of the plurality of signals has an edge to enable clock recovery at the second IC;
• a time difference between T2 and T3 is greater than both a time difference between T1 and T2 and also a time difference between T3 and T4;
• and
• no signal has edges at both T1 and T2 and no signal has edges at both T3 and T4.