Semiconductor circuit having a depression-type NMOS transistor provided on a power supply side
AssigneesKabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
InventorYutaka Okada
Life of this patent
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Abstract
A semiconductor circuit according to embodiments includes a circuit that includes the current source and generates the output voltage, and a voltage filter constituted by a depression-type NMOS transistor, the depression-type NMOS transistor having a source connected to a power supply side of the circuit, a gate that is grounded, and a drain to which a power supply voltage is applied. Thereby, a voltage on the power supply side of the circuit that has the current source and generates an output voltage is fixed regardless of an influence of a power supply fluctuation and suppresses a change in circuit characteristics.
Claims10
A semiconductor circuit comprising:
- a plurality of circuits including a current source and generating an output voltage;
- and
- at least one voltage filter constituted by a depression-type NMOS transistor, the depression-type NMOS transistor having a source commonly connected to a power supply side of the circuits, a gate that is grounded, and a drain to which a power supply voltage is applied.
A semiconductor circuit comprising:
- a first NMOS transistor having a source that is grounded, a gate to which an input voltage is applied, and a drain that is connected to an output terminal, the first NMOS transistor operating in a saturation region, and constituting a current source;
- a second NMOS transistor having a source connected to the output terminal, and a gate and a drain that are commonly connected, the second NMOS transistor operating in a saturation region;
- and
- a third NMOS transistor having a drain connected to a power supply terminal, a source connected to the gate and the drain of the second NMOS transistor, and a gate that is grounded, the third NMOS transistor being a depression-type.
A semiconductor circuit comprising:
- a first NMOS transistor having a source that is grounded, a gate to which a bias voltage is applied, and a drain that is connected to an output terminal, the first NMOS transistor operating in a saturation region, constituting a current source;
- a second NMOS transistor having a source connected to the output terminal, and a gate to which an input voltage is applied, the second NMOS transistor operating in a saturation region;
- and
- a third NMOS transistor having a drain connected to a power supply terminal, a source connected to a drain of the second NMOS transistor, and a gate that is grounded, the third NMOS transistor being a depression-type.
Dependencies are inferred from the claim text.