Method for forming nanosheet transistor structures

A method for forming a first and a second nanosheet transistor structure, each comprising a source, a drain, and a channel extending between the source and the drain in a first direction, and a gate extending across the channel, wherein the first and second nanosheet transistor structures are spaced apart in a second direction, transverse to the first direction, by an insulating wall extending in the first direction, and the method comprising:

• forming a first stack and a second stack separated by a trench extending in the first direction, each stack comprising a nanosheet intermediate a pair of sacrificial layers, wherein each nanosheet is formed of a channel material and each sacrificial layer is formed a sacrificial material;
• forming a recess in the first and second stacks, between the respective pairs of sacrificial layers, comprising etching back a respective inner sidewall surface of the nanosheets from the trench;
• forming the insulating wall between the first stack and the second stack, comprising depositing an insulating material filling the trench and the recesses;
• forming a sacrificial gate extending across the first stack, the insulating wall, and the second stack, thereby defining:
• at the first stack, a channel region of the first nanosheet transistor structure, and a source and a drain region of the first nanosheet transistor structure on either side of the channel region, and
• at the second stack, a channel region of the second nanosheet transistor structure, and a source and a drain region of the second nanosheet transistor structure on either side of the channel region,
• removing, from the first and second stacks in said source and drain regions, the sacrificial material and the channel material by etching;
• forming by epitaxy in the source and drain regions, the source and the drain of the first nanosheet transistor structure, and the source and the drain of the second nanosheet transistor structure;
• removing the sacrificial gate, thereby exposing the first and the second stacks in the respective channel regions;
• forming a respective channel portion of the first and second nanosheet transistor structure, comprising removing sacrificial material from the first and second stacks in the respective channel regions to expose upper and lower surfaces of a nanosheet portion of the respective nanosheets, each nanosheet portion having an etched-back inner sidewall surface abutting the insulating wall;
• and
• forming a respective gate stack for the first and second nanosheet transistor structures, wherein the nanosheet portion of the first nanosheet transistor structure extends through the first gate stack and the nanosheet portion of the second nanosheet transistor structure extends through the second gate stack.