Memory access system, method for controlling the same, computer-readable storage medium, and image forming apparatus
AssigneeCanon Kabushiki Kaisha
InventorsJunichi Goda, Yasushi Shinto
Life of this patent
Estimating the term…
Abstract
To accomplish this, this memory access system monitors a use-memory-bandwidth which indicates a total of memory bandwidths used between a memory and a plurality of masters, and determines whether the use-memory-bandwidth is equal to or larger than the first threshold. Based on the above-described determination result, this memory access system also restricts access to the memory by a master of low priority out of the plurality of masters.
Claims23
A memory access system comprising:
- a memory;
- an image processing unit that executes image processing;
- a scanner that reads an original and generates image data;
- a plurality of masters including at least a first master and a second master, the first master executing, via an internal bus, an access to the memory based on generation of image data by the scanner and the second master executing, via the internal bus, the access to the memory based on execution of image processing by the image processing unit;
- and
- a monitor unit that
- monitors a data amount, per predetermined time, transmitted via the internal bus in an access between each of the plurality of masters and the memory;
- and
- calculates a total of the data amounts, per predetermined time, of the plurality of masters;
- and
- a controller that reduces access to the memory via the internal bus by the second master among the plurality of masters and does not reduce access to the memory via the internal bus by the first master among the plurality of masters in a case where a predetermined condition regarding the total of the data amounts, per predetermined time, of the plurality of masters monitored by the monitor unit is satisfied.
A memory access system comprising:
- a memory;
- an image processing unit that executes image processing;
- a scanner that reads an original and generates image data;
- a plurality of masters including at least a first master and a second master, the first master executing, via an internal bus, an access to the memory based on generation of image data by the scanner and the second master executing, via the internal bus, the access to the memory based on execution of image processing by the image processing unit;
- a monitor unit that
- monitors a data amount, per predetermined time, transmitted via the internal bus in an access between each of the plurality of masters and the memory;
- and
- calculates a total of the data amount, per predetermined time, of the plurality of masters;
- and
- a memory controller that reduces access to the memory via the internal bus by the second master among the plurality of masters and does not reduce access to the memory via the internal bus by the first master in a case where a predetermined condition regarding the total of the data amounts, per predetermined time, of the plurality of the masters monitored by the monitor unit is satisfied.
An image forming apparatus comprising:
- a memory access system;
- an image processing unit that executes image processing;
- a scanner that reads an image from an original;
- and
- a printer that forms an image on a recording medium,
- wherein the memory access system comprises
- a memory;
- a plurality of masters including at least a first master and a second master, the first master executing, via an internal bus, an access to the memory based on generation of image data by the scanner and the second master executing, via the internal bus, the access to the memory based on execution of image processing by the image processing unit;
- a monitor unit that
- monitors a data amount, per predetermined time, transmitted via the internal bus in an access between each of the plurality of masters and the memory;
- and
- calculates a total of the data amount, per predetermined time, of the plurality of masters;
- and
- a controller that reduces access to the memory via the internal bus by the second master among the plurality of masters and does not reduce access to the memory via the internal bus by the first master among the plurality of masters in a case where a predetermined condition regarding the total of the data amounts, per predetermined time, of the plurality of masters monitored by the monitor unit is satisfied.
A method for controlling a memory access system that includes a memory, an image processing unit that executes image processing, a scanner that reads an original and generates image data, and a plurality of masters including at least a first master and a second master, the first master executing, via an internal bus, an access to the memory based on generation of image data by the scanner and the second master executing, via the internal bus, the access to the memory based on execution of image processing by the image processing unit, the method comprising executing:
- monitoring a data amount, per determined time, transmitted via the internal bus in an access between each of the plurality of masters and the memory
- calculating a total of the data amounts, per predetermined time, of the plurality of masters;
- and
- reducing access to the memory via the internal bus by the second master among the plurality of masters and not reducing access to the memory via the internal bus by the first master among the plurality of masters in a case where a predetermined condition regarding the total of the data amounts, per predetermined time, of the plurality of masters monitored by the monitor unit is satisfied.
A non-transitory computer-readable storage medium storing a computer program for causing a computer to execute respective steps in a method for controlling a memory access system that includes a memory, an image processing unit that executes image processing, a scanner that reads an original and generates image data, and a plurality of masters including at least a first master and a second master, the first master executing, via an internal bus, an access to the memory based on generation of image data by the scanner and the second master executing, via the internal bus, the access to the memory based on execution of image processing by the image processing unit,
- wherein the method executes
- monitoring a data amount, per determined time, transmitted via the internal bus in an access between each of the plurality of masters and the memory
- calculating a total of the data amounts, per predetermined time, of the plurality of masters and
- reducing access to the memory via the internal bus by the second master among the plurality of masters and not reducing access to the memory via the internal bus by the first master among the plurality of masters in a case where a predetermined condition regarding the total of the data amounts, per predetermined time, of the plurality of masters monitored by the monitor unit is satisfied.
Dependencies are inferred from the claim text.