Programmable-logic-directed multiplier mapping

Multiplier circuitry on an integrated circuit device, the multiplier circuitry comprising:

• first input circuitry configured to receive a first input having a first number of bits;
• second input circuitry configured to receive a second input having a second number of bits;
• first combinatorial circuitry coupled to the first input circuitry and the second input circuitry and configured to generate, based at least in part on the first input and the second input, a first subset of two or more partial products, wherein each of the two or more partial products comprises a respective product of bitwise multiplication of a respective bit of the second number of bits with each of the first number of bits, wherein the first combinatorial circuitry is configured to perform a combinatorial function to generate the first subset based at least in part on redundant form arithmetic;
• and
• carry chain circuitry, comprising:
• second combinatorial circuitry coupled to the first input circuitry and the second input circuitry and configured to generate, based at least in part on the first input and the second input, a second subset of the two or more partial products;
• and
• one or more binary adders coupled to the second combinatorial circuitry, wherein the one or more binary adders are configured to generate a product based at least in part on a sum of the first subset and the second subset;
• wherein one or both of the second combinatorial circuitry or the one or more binary adders are configured to receive the first subset from the first combinatorial circuitry.

A tangible, non-transitory, machine-readable medium, comprising machine-readable instructions to construct multiplier circuitry that, when executed by one or more processors, cause the one or more processors to:

• configure first combinatorial circuitry to perform a combinatorial function, based at least in part on redundant form arithmetic, to generate a first subset of two or more partial products, wherein the two or more partial products are based at least in part on a first input to the multiplier circuitry and a second input to the multiplier circuitry;
• configure second combinatorial circuitry of a carry chain in the multiplier circuitry to generate a second subset of the two or more partial products based at least in part on the first input and the second input;
• and
• configure one or more binary ripple-carry adders of the carry chain to generate a product of the multiplier circuitry based at least in part on a sum of the two or more partial products.