Background calibration of non-linearity of samplers and amplifiers in ADCs
AssigneeAnalog Devices, Inc.
InventorsAhmed Mohamed Abdelatty Ali, Paridhi Gulati
Life of this patent
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Abstract
Analog circuits are often non-linear, and the non-linearities can hurt performance. Designers would trade off power consumption to achieve better linearity. An efficient and effective calibration technique can address the non-linearities and reduce the overall power consumption. A dither signal injected to the analog circuit can be used to expose the non-linear behavior in the digital domain. To detect the non-linearities, a counting approach is applied to isolate non-linearities independent of the input distribution. The approach is superior to and different from other approaches in many ways.
Claims20
A method for efficient error estimation and calibration of a circuit, comprising:
- adding a dither at an input of the circuit;
- removing the dither at an output of the circuit;
- determining a sign bit of the dither;
- determining whether a given sample of the output is within a first range on the output defined by a first inspection point;
- determining whether the given sample of the output is within a second range on the output defined by a second inspection point;
- determining a first partial error by logically combining the sign bit of the dither and whether the given sample of the output is within the first range;
- determining a second partial error by logically combining the sign bit of the dither and whether the given sample of the output is within the second range;
- updating an estimate of a component of a circuit on a sample-by-sample basis based on the first partial error and the second partial error;
- and
- calibrating the circuit based on the estimate of the component of the circuit.
A calibration system with efficient error estimation, comprising:
- dither circuitry to inject a dither at an input of a circuit and to remove the dither at an output of the circuit;
- a first operation to determine whether a corrected output of the circuit is within a first range defined by a first inspection point;
- a second operation to obtain a sign of the dither;
- a third operation to obtain a first partial error at the first inspection point by logically combining outputs of the first operation and the second operation;
- and
- calibration circuitry to update an estimate of a component of the circuit based on the first partial error at the first inspection point and a second partial error, wherein the second partial error is based on a second inspection point and the sign of the dither.
A calibration system with efficient error estimation, comprising:
- dither circuitry to inject a dither at an input of a circuit and to remove the dither at an output of the circuit;
- error circuitry to:
- compute a first partial error by logically combining a sign bit of the dither and whether a given sample of the output is within a first range on the output defined by a first inspection point;
- compute a second partial error by logically combining a sign bit of the dither and whether the given sample of the output is within a second range on the output defined by a second inspection point;
- and
- calibration circuitry to update an estimate of a component of the circuit based on the first and second partial errors computed for successive samples of the output of the circuit.
Dependencies are inferred from the claim text.