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US 11,158,620 B2Granted
Wafer bonding in fabrication of 3-dimensional NOR memory circuits
AssigneeSunrise Memory Corporation
InventorsScott Brad Herner, Eli Harari
Life of this patent
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Abstract
A memory array and single-crystal circuitry are provided by wafer bonding (e.g., adhesive wafer bonding or anodic wafer bonding) in the same integrated circuit and interconnected by conductors of an interconnect layer. Additional circuitry or memory arrays may be provided by additional wafer bonds and electrically connected by interconnect layers at the wafer bonding interface. The memory array may include storage or memory transistors having single-crystal epitaxial silicon channel material.
Claims11
An integrated circuit, comprising:
- a monocrystalline semiconductor substrate;
- a first set of circuitry comprising single-crystal transistors formed in the semiconductor substrate;
- a first interconnect layer comprising a plurality of conductors that are formed on top of the circuitry;
- a first memory block electrically connected to the first set of circuitry through the conductors in the first interconnect layer, wherein the conductors in the first interconnect layer and the first memory block are joined by wafer-bonding;
- a second interconnect layer formed above the first memory block, wherein the second interconnect layer includes a plurality of conductors and wherein the first and second interconnect layers are provided on opposite sides of the first memory block;
- a second set of circuitry, formed in a silicon layer that is provided on an insulator layer of a silicon-on-insulator wafer, wherein the second set of circuitry comprises single-crystal transistors, wherein the second set of circuitry is electrically connected to the first memory block through the conductors in the second interconnect layer, and wherein the second set of circuitry and the conductors in the second interconnect layer are joined by wafer bonding;
- and
- a third interconnect layer, wherein the third interconnect layer comprises a plurality of conductors and is provided on a side of the insulator layer opposite the silicon layer on which the second set of circuitry is formed.
5 more elements
Dependencies are inferred from the claim text.