Dynamic vision sensor device including buffer

A dynamic vision sensor device comprising:

• a photo detector configured to output a detection signal based on incident light;
• a log amplifier configured to receive the detection signal from the photo detector through a first node, to amplify the detection signal and thereby generate an amplified detection signal, and to output the amplified detection signal to a second node;
• a differencing amplifier configured to output a difference signal based on a change in an intensity of the amplified detection signal;
• and
• an event determination circuit configured to determine an event based on the difference signal, wherein:
• the log amplifier includes:
• a first transistor connected between a power node and a third node, and configured to operate in response to a voltage of the first node;
• a second transistor connected between the second node and a ground node and configured to operate in response to a voltage of the third node;
• and
• a third transistor connected between the power node and the first node and configured to operate in response to a voltage of the second node.

A dynamic vision sensor device comprising:

• a photo detector configured to output a detection signal based on incident light;
• a log amplifier configured to receive the detection signal from the photo detector through a first node, to amplify the detection signal and thereby generate an amplified detection signal, and to output the amplified detection signal to a second node;
• a differencing amplifier configured to output a difference signal based on a change in an intensity of the amplified detection signal;
• and
• an event determination circuit configured to determine an event based on the difference signal, wherein:
• the log amplifier further includes:
• a first transistor connected between a third node and a ground node and configured to operate in response to a voltage of the first node;
• a second transistor connected between a power node and the second node, and configured to operate in response to a voltage of the third node;
• and
• a third transistor connected between the power node and the first node and configured to operate in response to a voltage of the second node.