Two dimensional shift array for image processor
AssigneeGoogle Inc.
InventorsOfer Shacham, Jason Rupert Redgrave, Albert Meixner, Qiuling Zhu, Daniel Frederic Finchelstein, David Patterson, Donald Stark
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Abstract
An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.
Claims20
A processor comprising:
- a plurality of execution lanes, each execution lane comprising logic circuitry configured to execute instructions of an instruction set architecture for the processor;
- and
- a two-dimensional shift-register array comprising a plurality of shift registers that are each dedicated to a respective execution lane of the plurality of execution lanes, wherein each shift register of the plurality of shift registers in the shift-register array is coupled to a respective adjacent shift register in a same row or column of the shift-register array and to at least one respective nonadjacent shift register in the same row or column of the shift-register array,
- wherein the plurality of execution lanes are configured to execute a first instruction that causes each shift register to shift data to a respective adjacent shift register in the same row or column of the shift-register array, and to execute a second instruction having an operand that specifies a shift amount for shifting data to nonadjacent shift registers, wherein the second instruction causes each shift register to shift data by the specified shift amount to a respective nonadjacent shift register in the same row or column of the shift-register array.
A method performed by a processor comprising a plurality of execution lanes and a two-dimensional shift-register array comprising a plurality of shift registers that are each dedicated to a respective execution lane of the plurality of execution lanes, wherein each shift register of the plurality of shift registers in the shift-register array is coupled to a respective adjacent shift register in a same row or column of the shift-register array and to at least one respective nonadjacent shift register in the same row or column of the shift-register array, the method comprising:
- executing, by the plurality of execution lanes, instructions of an instruction set architecture for the processor, including:
- executing a first instruction that causes each shift register to shift data to a respective adjacent shift register in a same row or column of the shift-register array, and
- executing a second instruction having an operand that specifies a shift amount for shifting data to nonadjacent shift registers, wherein the second instruction causes each shift-register to shift data by the specified shift amount to a respective nonadjacent shift register in the same row or column of the shift-register array.
One or more non-transitory computer storage media encoded with instructions that when executed by a processor comprising:
- a plurality of execution lanes and a two-dimensional shift-register array comprising a plurality of shift registers that are each dedicated to a respective execution lane of the plurality of execution lanes, wherein each shift register of the plurality of shift registers in the shift-register array is coupled to a respective adjacent shift register in a same row or column of the shift-register array and to at least one respective nonadjacent shift register in the same row or column of the shift-register array,
- cause the processor to perform operations comprising:
- executing, by the plurality of execution lanes, instructions of an instruction set architecture for the processor, including:
- executing a first instruction that causes each shift register to shift data to a respective adjacent shift register in a same row or column of the shift-register array, and
- executing a second instruction having an operand that specifies a shift amount for shifting data to nonadjacent shift registers, wherein the second instruction causes each shift-register to shift data by the specified shift amount to a respective nonadjacent shift register in the same row or column of the shift-register array.
Dependencies are inferred from the claim text.