Data packet processing system on a chip
AssigneeMaxLinear, Inc.
InventorsIngo Volkening, Hak Keong Sim, Ritesh Banerjee
Life of this patent
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Abstract
An on-chip data packet processing method and corresponding integrated circuit, wherein data packets are received at an ingress port and processed with an on-chip wire-speed engine. The processing comprises adding metadata to the data packets, forwarding the processed data to an on-chip QoS unit, altering the metadata of the data packets and/or providing further metadata to the data packets. The data packets are forwarded from the on-chip QoS unit to an on-chip data consumer. If the data consumer is a processing unit the data packets are processed in a first processing step, redirected from the processing unit to the QoS unit and the step of forwarding the data packets to an on-chip data consumer is repeated.
Claims15
An on-chip data packet processing method comprising
- receiving data packets at an ingress port,
- processing the data packets with an on-chip wire-speed engine, the processing comprising adding metadata to the data packets to form transformed data packets,
- forwarding the transformed data packets to a first entrance to an on-chip Quality of Service (QoS) circuit,
- modifying the metadata of the transformed data packets by providing further metadata to the transformed data packets or altering the metadata of the transformed data packets,
- forwarding the modified, transformed data packets from the on-chip QoS circuit to an on-chip data consumer, the on-chip data consumer being selected from an egress port, a switch, and a processing unit, the type of the on-chip data consumer being dependent on the modified metadata, and
- if the modified, transformed data packets are forwarded to a processing circuit:
- processing the modified, transformed data packets in a first processing step to form processed data,
- redirecting the processed data from the processing circuit back to a second entrance to the QoS circuit, and
- repeating the act of forwarding the processed data to a data consumer.
An integrated circuit, the integrated circuit comprising
- a wire speed engine circuit configured to process data packets, by providing metadata to the data packets to form transformed data packets, wherein the wire speed engine circuit is connected to one or more ingress ports,
- a Quality of Service (QoS) circuit configured to modify the metadata of the transformed data packets, the modifying comprising providing further metadata to the transformed data packets or altering the metadata of the transformed data packets, the QoS circuit being connected to the wire speed engine circuit, the QoS circuit having two or more entrances to the QoS circuit,
- at least one microprocessor configured to process the modified, transformed data packets, the processing being dependent on the modified metadata, and
- one or more egress ports, the egress ports being connected to the QoS circuit and/or to the at least one microprocessor, wherein the microprocessor is operable to:
- process the data packets in a first processing step, and
- redirect the processed data from the processing unit to the QoS circuit and forward the data packets to a data consumer.
Dependencies are inferred from the claim text.