Decision feedback equalizer
AssigneeMicron Technology, Inc.
InventorsJennifer E. Taylor, Raghukiran Sreeramaneni
Life of this patent
Estimating the term…
Abstract
A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.
Claims20
A device, comprising:
- a channel transmitting a first bit, a second bit, a third bit, and a fourth bit in sequence;
- a deserializer;
- and
- a first circuit, a second circuit, a third circuit, and a fourth circuit coupled in parallel between the channel and the deserializer;
- wherein the first circuit is configured to receive the first bit and output a fifth bit to the deserializer;
- wherein the second circuit is configured to receive the second bit and output a sixth bit, which distortion is corrected based at least in part on the fifth bit, to the deserializer;
- wherein the third circuit is configured to receive the third bit and output a seventh bit, which distortion is corrected based at least in part on the sixth bit, to the deserializer;
- and
- wherein the fourth circuit is configured to receive the fourth bit and output an eighth bit, which distortion is corrected based at least in part on the seventh bit, to the deserializer.
A method, comprising:
- receiving a first bit along a first data channel;
- receiving a second bit along a second data channel after receiving the first bit;
- receiving a third bit along a third data channel after receiving the second bit;
- receiving a fourth bit along a fourth data channel after receiving the third bit;
- outputting a fifth bit along a fifth data channel that is distortion corrected based at least in part on the first bit;
- outputting a sixth bit along a sixth data channel, wherein the sixth bit is distortion corrected based at least in part on the fifth bit;
- outputting a seventh bit along a seventh data channel, wherein the seventh bit is distortion corrected based at least in part on the sixth bit;
- and
- outputting an eighth bit along an eighth data channel, wherein the eighth bit is distortion corrected based at least in part on the seventh bit.
A device comprising:
- a channel configured to transmit a first bit, a second bit, a third bit and a fourth bit in sequence;
- deserializer configured to output a plurality of adjustment signals;
- and
- a plurality of circuits coupled in parallel between the channel and the deserializer, wherein a first circuit of the plurality of circuits is configured to:
- receive the first bit from the channel;
- generate a fifth bit based at least in part on the first bit, wherein the fifth bit is distortion corrected based at least in part on the first bit;
- and
- output the fifth bit to the deserializer;
- and
- wherein a second circuit of the plurality of circuits is configured to:
- receive the second bit from the channel;
- receive a first adjustment signal associated with the fifth bit from the deserializer;
- generate a sixth bit based at least in part on the second bit, wherein the sixth bit is distortion corrected based at least in part on the fifth bit;
- and
- output the sixth bit to the deserializer.
Dependencies are inferred from the claim text.