Feedforward equalizer with programmable roaming taps

A method of operating a transmit-side feedforward equalizer, said method comprising:

• serializing input digital data bits received in parallel at a first re-timer and multiplexor circuit stage of a first data serializer circuit comprising a first plurality of pipeline connected re-timer and multiplexor circuit stages, each successive re-timer and multiplexor stage of said first plurality reducing the number of parallel digital bits output at each respective successive stage in accordance with a respective received different binary frequency scaled clock signal, the respective received different binary frequency scaled clock signal being a scaled sub-multiple of an input clock signal;
• serializing the input digital data bits received in parallel at a first re-timer and multiplexor circuit stage of a second data serializer circuit in parallel with said first data serializer circuit, the second data serializer circuit comprising a second plurality of pipeline connected re-timer and multiplexor circuit stages in one-to-one correspondence with said first plurality of pipeline connected re-timer and multiplexor circuit stages, said second data serializer providing a second data output delayed in time according to a programmed latency with respect to an output of said first data serializer circuit;
• and
• programming a time delay latency of said second data output of said second data serializer circuit using a plurality of programmable switching devices in one-to-one correspondence with said second plurality of pipeline connected re-timer and multiplexor stages, each respective programmable switching device receiving a respective different binary frequency scaled clock signal or its complement binary frequency scaled clock signal,
• each of said plurality of programmable switching devices programmed to select an output of one of:
• a binary frequency scaled clock signal or its complement binary frequency scaled clock signal for receipt at its corresponding re-timer and multiplexor stage of said second plurality,
• wherein the programmed time delay latency of said second data serializer circuit output relative to said first data serializer circuit output is one of:
• k unit intervals when the input clock signal is a full rate clock signal, or k=jN when the input clock signal is 1/N rate of the full rate clock signal, a unit interval corresponding to a duration of time of a pulse or symbol in an output data stream, and where k, j are whole numbers and N is a positive integer.