Chip to chip time synchronization

An apparatus, comprising:

• a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal;
• a second IC chip configured to receive the timing signal from the first IC chip and the reference clock signal;
• and
• a third IC chip configured to receive the timing signal from the second IC chip and the reference clock signal, wherein the second IC chip is electrically coupled between the first and third IC chips,
• wherein the first, second, and third IC chips are configured to generate respective first, second, and third reference time signals based on the timing signal and the reference clock signal, and wherein each of the first, second, and third reference time signals is associated with a count of a number of cycles of the reference clock signal starting from a same particular cycle of the reference clock signal, wherein a time synchronization of operations in the first, second, and third IC chips is performed with a higher accuracy of each other based on use of the first, second, and third reference time signals, respectively, than with use of the reference clock signal.

An apparatus comprising:

• a first integrated circuit (IC) chip configured to receive a timing signal and a first reference clock signal;
• a second IC chip configured to receive the timing signal from the first IC chip and the first reference clock signal;
• and
• a third IC chip configured to receive the timing signal from the second IC chip and the first reference clock signal, wherein the second IC chip is electrically coupled between the first and third IC chips,
• wherein an IC chip comprising one of the first, second, or third IC chip is configured to generate, based on the timing signal and the first reference clock signal, a first reference time signal indicative of a count of cycles of the first reference clock signal, wherein the IC chip includes a reference clock that generates a second reference clock signal at a higher frequency than the first reference clock signal, and wherein the IC chip is configured to generate, based on the first reference time signal and the second reference clock signal, a second reference time signal indicative of a count of cycles of the second reference clock signal.

An apparatus comprising:

• a first reference clock configured to generate a first reference clock signal;
• and
• an integrated circuit (IC) chip electrically coupled with the first reference clock, the IC chip configured to receive the first reference clock signal from the first reference clock and a timing signal,
• wherein the IC chip includes a first counter configured to generate, based on the timing signal and the first reference clock signal, a first reference time signal indicative of a count of periods of the first reference clock signal,
• wherein the IC chip includes a second reference clock configured to generate a second reference clock signal having a second frequency different from a first frequency associated with the first reference clock signal,
• wherein the IC chip includes a clock generator configured to generate, based on the first reference clock signal, the second reference clock signal, and a phase selection, a third reference clock signal having a third frequency or phase shift different from the second reference clock signal, and
• wherein the IC chip includes a second counter configured to generate a third reference time signal indicative of sub-periods of the third reference clock signal in accordance with the phase selection.