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US 11,153,032 B2Granted
Forward error correction mechanism for peripheral component interconnect-express (PCI-E)
AssigneeIntel Corporation
InventorDebendra Das Sharma
Life of this patent
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Abstract
Aspects of the embodiments are directed to systems, methods, and devices that can activate forward error correction (FEC) based on the channel loss of a channel. The channel's loss can be characterized as a high loss channel if the channel loss exceeds a predetermined threshold value. For channels with high loss and for those that operate at high data rates (e.g., data rates commensurate with PCIe Gen 4 or Gen 5), FEC can be activated so that the channels can achieve higher data rates.
Claims20
An apparatus comprising:
- a downstream port to transmit data blocks across a link, the downstream port comprising circuitry to:
- change a first data rate of 64 gigatransfers per second (GT/s) to a second data rate, the second data rate lower than 64 GT/s;
- determine error correcting code (ECC) for the data block;
- transmit the data block with the ECC at the second data rate below 64 GT/s;
- and
- transmit a skip ordered set (SKP OS) across the link without ECC.
3 more elements
A method comprising:
- determining that a data rate for transmitting data blocks across a link is to change from 64 gigatransfers per second (GT/s) to a data rate below 64 GT/s;
- activating forward error correction for the data blocks;
- transmitting the data blocks with forward error correction at the data rate below 64 GT/s;
- and
- transmitting skip ordered set (SKP OS) after the data blocks without forward error correction.
2 more elements
A system comprising:
- a host device comprising:
- a downstream port comprising circuitry to transmit data blocks across a link, the downstream port comprising circuitry to:
- determine that a first data rate for transmitting data blocks across a link is to change from 64 gigatransfers per second (GT/s) to a second data rate below 64 GT/s;
- activate forward error correction for the data blocks;
- transmit the data blocks with forward error correction at the second data rate below 64 GT/s;
- transmit skip ordered set (SKP OS) after the data blocks without forward error correction.
3 more elements
Dependencies are inferred from the claim text.