Very low complexity SECDED codes
AssigneeWestern Digital Technologies, Inc.
InventorIshai Ilani
Life of this patent
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Abstract
A data storage device has a controller that is configured to generate SECDED codes based on a plurality (at least 2) of codes, where each of the constituent codes is a cyclic code over a finite field of size 2m for some integer m. Any 2 constituent codes are associated with 2m1 and 2m2, where m1 and m2 are coprime (i.e., gcd(m1,m2)=1) where gcd is the greatest common divisor. In such a case, it is possible to generate a cyclic code of length (2m1−1)*(2m2−1), which will be a long code, but enjoy the complexity, in encoding and decoding, of the small fields of the constituent codes.
Claims20
A data storage device, comprising:
- a memory device;
- and
- a controller coupled to the memory device, the controller configured to:
- retrieve a codeword from the memory device;
- determine a first Galois Field GF(2m1) and a second Galois Field GF(2m2) for the codeword, wherein m1+m2+1=m and m is an integer;
- generate a single error correcting cyclic code of a first length;
- generate a SECDED cyclic code of a second length, wherein the second length is different from the first length;
- generate a first binary matrix corresponding to the single error correcting cyclic code;
- generate a second binary matrix corresponding to the SECDED cyclic code;
- generate a parity check matrix;
- rotate the single error correcting cyclic code of the first length until either an error is present in the parity check matrix or a first number of rotations has occurred, wherein the first number of rotations corresponds to a number of parity bits of the parity check matrix divided by a number of bits of data of the single error cyclic code;
- rotate the SECDED cyclic code of the second length until either the error is present in the parity check matrix or a second number of rotations has occurred, wherein the second number of rotations corresponds to the number of parity bits of the parity check matrix divided by a number of bits of data of the SECDED cyclic code;
- and
- upon determining a location of the error, flip a bit corresponding to the location.
A data storage device, comprising:
- a memory device;
- and
- a controller coupled to the memory device, the controller configured to:
- retrieve a codeword from the memory device;
- generate two constituent codes of unequal length from the codeword of a first length;
- rotate at least one constituent code of the two constituent codes until either an error within the at least one constituent code is present in a parity portion or a number of rotations has occurred, wherein the number of rotations corresponds to a number of parity bits of the parity check matrix divided by a number of bits of data of the at least one constituent code;
- determine a location of the error;
- upon determining the location of the error, flip a bit corresponding to the location;
- and
- decode the codeword.
A data storage device, comprising:
- a memory device;
- means to retrieve codewords from the memory device;
- means to generate a cyclic code with the codewords of an odd integer weight using Chinese Remainder Theorem (CRT), wherein the means to generate are coupled to the memory device;
- means to determine a location of an error in the cyclic code;
- and
- upon determining the location of the error, means to flip a bit corresponding to the location.
Dependencies are inferred from the claim text.