Decoding method and storage controller

A storage controller, configured to control a storage device having a rewritable non-volatile memory module, the storage controller comprising:

• a memory interface control circuit, configured to couple to the rewritable non-volatile memory module,
• an error checking and correcting circuit comprising a decoder controller and a plurality of circuits coupled to the decoder controller;
• and
• a processor, coupled to the error checking and correcting circuit and the memory interface control circuit, wherein the memory interface control circuit transmits a codeword read from the rewritable non-volatile memory module to the error checking and correcting circuit,
• wherein the error checking and correcting circuit is configured to receive the codeword, group a plurality of data bits of the codeword into a plurality of data bit value sets, and perform a decoding operation on the plurality of data bit value sets, wherein in the performed decoding operation, the error checking and correcting circuit is configured to perform following operations:
• step (1) the error checking and correcting circuit is configured to sequentially perform a plurality of syndrome calculation operations respectively on the plurality of data bit value sets by using a plurality of parity check sub-matrices of a parity check matrix, so as to obtain a plurality of temporary syndromes respectively corresponding to the plurality of data bit value sets, and perform a step (2) after all the plurality of temporary syndromes respectively corresponding to the plurality of data bit value sets are obtained;
• step (2) the error checking and correcting circuit is configured to determine whether the codeword is correct or incorrect according to the latest obtained plurality of temporary syndromes, wherein if the codeword is determined as correct, the decoding operation is completed and the data bits are outputted, wherein if the codeword is determined as incorrect, a step (3) is performed to start one new iterative operation;
• step (3) the error checking and correcting circuit is configured to sequentially perform a plurality of error function calculations according to the plurality of temporary syndromes, so as to sequentially obtain a plurality of error value sets respectively corresponding to the plurality of data bit value sets, wherein in response to obtaining a first error value set, steps (4) and (5) are performed simultaneously;
• step (4) the error checking and correcting circuit is configured to sequentially perform a plurality of extreme value search operations on the error value sets to identify a target extreme value from all error values in the error value sets, and set a second error threshold for a next iterative operation according to the target extreme value;
• step (5) the error checking and correcting circuit is configured to sequentially perform a plurality of bit-flipping operations respectively on the plurality of data bit value sets according to a first error threshold for a current iterative operation and the error value sets so as to update the plurality of data bit value sets as updated data bit value sets, wherein if the current iterative operation is a first iterative operation, the first error threshold for the current iterative operation is a predetermined error threshold, wherein if the current iterative operation is not the first iterative operation, the first error threshold for the current iterative operation is an error threshold identified in a previous iterative operation, wherein in response to completing a first bit-flipping operation, a step (6) is performed simultaneously,
• wherein the error checking and correcting circuit is configured to perform an error function calculation on a second data bit value set to obtain a second error value set corresponding to the second data bit value set, an extreme value search operation of a first data bit value set, and the first bit-flipping operation on the first error value set simultaneously to shortened the decoding operation on the plurality of data bit value sets stored in the non-transitory rewritable non-volatile memory;
• step (6) the error checking and correcting circuit is configured to sequentially perform a plurality of syndrome calculation operations respectively on the updated data bit value sets by using the parity check sub-matrices, so as to obtain an updated plurality of temporary syndromes respectively corresponding to the updated data bit value sets, wherein in response to obtaining all the plurality of temporary syndromes respectively corresponding to the updated data bit value sets, the error checking and correcting circuit is configured to complete the current iterative operation and perform the step (2), wherein each of said iterative operations comprises the steps (2) to (6), wherein the updated data bit value sets, the corresponding plurality of temporary syndromes and the first error threshold obtained from the current iterative operation are used in the next iterative operation,
• wherein in the operation of the step (2),
• the error checking and correcting circuit is configured to sequentially perform an XOR calculation on the plurality of temporary syndromes to obtain a final syndrome,
• wherein if a plurality of values of the final syndrome are all zero, the error checking and correcting circuit is configured to determine the codeword as correct,
• wherein if the values of the final syndrome are not all zero, the error checking and correcting circuit is configured to determine the codeword as incorrect.