Back to results
US 11,152,947 B2Granted
Feedback control for accurate signal generation
AssigneeRenesas Electronics America Inc.
InventorMin Chu
Life of this patent
Estimating the term…
Abstract
A phase-locked loop (PLL) performs hitless switching from a first reference clock (ref1) to a second reference clock (ref2) by entering holdover mode (418), and aligning the feedback clock (fbclk) to the second reference clock while in holdover mode. The alignment is performed by adjusting a divisor input (D) for the multi-mode divider (128) that divides the output clock frequency (PLLout) to generate the feedback clock. Other features are also provided.
Claims20
A method for operating a phase-locked loop (PLL), the method comprising:
- (1) operating the PLL from a first reference clock;
- and then
- (2) switching the PLL from the first reference clock to a second reference clock;
- and
- (3) operating the PLL from the second reference clock;
- wherein operating the PLL from a reference clock which is either one of the first and second reference clocks, comprises generating a PLL output signal and generating a feedback signal from the PLL output signal, wherein generating the PLL output signal comprises;
- generating, by a first circuit, a first error signal, wherein:
- in operation (1), the first error signal is indicative of an alignment between the first reference clock and the feedback signal;
- in operation (3), the first error signal is indicative of an alignment between the second reference clock and the feedback signal;
- and
- generating the PLL output signal responsively to the first error signal;
- wherein switching the PLL from the first reference clock to the second reference clock comprises:
- placing the PLL in holdover mode, in which the PLL output signal is generated independently from the first and second reference clocks;
- while in the holdover mode, controlling generation of the feedback signal from the PLL output signal responsively to a second error signal indicative of an alignment between the second reference clock and the feedback signal, the second error signal being generated by a second circuit.
11 more elements
A phase-locked loop (PLL) comprising:
- a first feedback loop for generating a PLL output signal responsively to a first error signal indicative of an alignment between a feedback signal and any selected first one of a plurality of reference clocks, wherein the feedback signal is to be generated by the PLL from the PLL output signal and a divisor signal controlling a frequency of the feedback signal based on a frequency of the PLL output signal, the first feedback loop comprising a first circuit configured to generate the first error signal;
- a second feedback loop for generating the divisor signal responsively to a second error signal indicative of an alignment between the feedback signal and any second one of the plurality of the reference clocks when the PLL is in holdover mode, the second feedback loop comprising a second circuit configured to generate the second error signal;
- wherein in normal mode, the first feedback loop is closed and the second feedback loop is open;
- wherein in the holdover mode, the first feedback loop is open and the second feedback loop is closed.
1 more element
Dependencies are inferred from the claim text.