Three-input exclusive NOR/OR gate using a CMOS circuit

A Complementary Metal Oxide Semiconductor (CMOS) transistor circuit configured to implement an exclusive NOR (XNOR) function comprising:

• a first block configured to generate a first output signal corresponding to a NOR gate logic state, in response to a first input signal and a second input signal;
• a second block comprising a first AND-OR gate connected with an output node of the first block, wherein the second block is configured to generate a second output signal corresponding to an OR gate logic state or an AND gate logic state, wherein the second block is configured to receive the first input signal, the second input signal and the first output signal of the first block;
• a third block connected with an output node of the second block, wherein the third block is configured to generate a third output signal corresponding to the NOR gate logic state, in response to a third input signal and the second output signal of the second block;
• a fourth block comprising a second AND-OR gate circuit connected with an output node of the third block, wherein the fourth block is configured to generate a fourth output signal corresponding to the OR gate logic state or the AND gate logic state in response to the third input signal, the second output signal of the second block and the third output signal of the third block;
• and
• a fifth block comprising an inverter gate circuit connected with an output node of the fourth block, wherein the fifth Hock is configured to generate a fifth output signal in response to the fourth output signal of the fourth block,
• wherein the first block comprises first and second p-channel Metal Oxide Semiconductor (PMOS) transistors in series and first and second n-channel Metal Oxide transistors in parallel, wherein the second PMOS transistor is directly connected to a power supply voltage.