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US 11,152,941 B2Granted
High-voltage voltage level converter
OwnerVladimir Vladimirovich Shubininventor
Life of this patent
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Abstract
The invention relates to a high-voltage voltage level converter for matching of the components of electronic systems containing multiple power sources. In particular, the high-voltage voltage level converter includes seven P-type field-effect transistors and seven N-type field-effect transistors, the signal input terminal (IN), the inputs of reference source voltages ⅔VDD) and (⅓VDD), inverted output, high-level source voltage terminals (VCC) and (VDD), and low-level source voltage terminal (VSS).
Claims1
High-voltage voltage level converter containing:
- P-type field-effect transistors (FETs) numbered from first to seventh and N-type FETs numbered from eighth to fourteenth;
- signal input terminal (IN) connected to gates of the first, eighth and fourteenth transistors;
- a high-level voltage power terminal (VDD) connected to source and substrate of the first transistor;
- a high-level voltage power terminal (VDD) connected to sources and substrates of the second and third transistors;
- a low-level voltage power terminal (VSS) connected to sources of the eighth, thirteenth and fourteenth transistors and substrates of transistors numbered from the eighth to the fourteenth;
- an inverted output (OUT) connected to drains of the seventh and tenth transistors, an input of reference source voltage (⅔VDD) connected to gates of the fourth, fifth, ninth and tenth transistors;
- an input of reference source voltage (⅓VDD) connected to gates of the sixth, seventh, eleventh and twelfth transistors,
- wherein drains of the first and eighth transistors are connected to a gate of the thirteenth transistor,
- a drain of the second transistor is connected to a source and a substrate of the fourth transistor, a drain of which is connected to a source and a substrate of the sixth transistor,
- a drain of the sixth transistor is connected to a drain of the ninth transistor,
- a drain of the third transistor is connected to a source and a substrate of the fifth transistor, a drain of which is connected to a source and a substrate of the seventh transistor,
- a source of the ninth transistor is connected to a drain of the eleventh transistor, a source of which is connected to a drain of the thirteenth transistor,
- a source of the tenth transistor is connected to a drain of the twelfth transistor, a source of which is connected to a drain of the fourteenth transistor, and
- wherein a gate of the second transistor is connected to drains of the seventh and tenth transistors, which connected to the inverted output (OUT), and
- a gate of the third transistor is connected to drains of the sixth and ninth transistors OUT.
12 more elements
Dependencies are inferred from the claim text.