Input buffer
AssigneeAnalog Devices, Inc.
InventorLawrence A. Singer
Life of this patent
Estimating the term…
Abstract
The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology.
Claims20
An input buffer comprising:
- an input to receive a voltage input signal;
- a first transistor of a first type;
- a second transistor of a second type complementary to the first type, wherein a source of the second transistor is coupled to a source of the first transistor;
- a third transistor of the second type in cascode configuration with the second transistor;
- an output at the sources of the first transistor and the second transistor;
- a first level shifter to generate a first level shifted voltage that follows the voltage input signal, and to set a voltage difference between a gate of the first transistor and a gate of the second transistor;
- and
- a second level shifter to generate a second level shifted voltage that follows the voltage input signal to maintain a constant drain to source voltage across the second transistor while the voltage input signal moves up and down and to bias the third transistor.
A method for buffering a voltage input signal, the method comprising:
- generate a first voltage shifted signal that follows the voltage input signal;
- biasing, based the first voltage shifted signal, a first transistor of a first type;
- biasing, based on the voltage input signal, a second transistor of a second type complementary to the first type;
- biasing, by a second voltage shifted signal, a cascode transistor of the second type coupled to the second transistor, wherein the second voltage shifted signal follows the voltage input signal to maintain a constant drain to source voltage across the second transistor while the voltage input signal moves up and down;
- and
- outputting, by sources of the first transistor and the second transistor, a voltage output signal.
An input buffer comprising:
- an input to receive a voltage input signal;
- a first transistor of a first type;
- a second transistor of a second type complementary to the first type, wherein a source of the second transistor is coupled to a source of the first transistor;
- an output at the sources of the first transistor and the second transistor;
- a third transistor of the second type in cascode configuration with the second transistor;
- a first level shifter to generate a first level shifted voltage that follows the voltage input signal independent of a frequency of the voltage input signal, and to bias the first transistor;
- and
- a second level shifter to generate a second level shifted voltage that follows the voltage input signal to maintain a constant drain to source voltage across the second transistor while the voltage input signal moves up and down, and to bias the third transistor.
Dependencies are inferred from the claim text.