Apparatuses for duty cycle adjustment of a semiconductor device
AssigneeMicron Technology, Inc.
InventorDean D. Gans
Life of this patent
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Abstract
Embodiments of the disclosure are drawn to apparatuses and methods for lookahead duty cycle adjustment of a clock signal. Clock signals may be provided to a semiconductor device, such as a memory device, to synchronize one or more operations. A duty cycle adjuster (DCA) of the device may adjust the clock signal(s) based on a duty code determined during an initialization of the device. While the device is in operation, a lookahead DCA (LA DCA) may test a number of different adjustments to the clock signal(s), the results of which may be determined by a duty cycle monitor (DCM). The results of the DCM may be used to select one of the tested adjustments, which may be used to update the duty code.
Claims22
An apparatus comprising:
- an upper duty cycle adjustor (DCAU) configured to adjust an upper clock signal based on an upper duty cycle adjustor (DCA) code, wherein the upper clock signal is associated with an upper byte of data;
- a lower duty cycle adjustor (DCAL) configured to adjust a lower clock signal based on a lower DCA code, wherein the lower adjusted clock signal is associated with a lower byte of data;
- an upper lookahead duty cycle adjustor (LA DCA) configured to adjust the upper clock signal based on a value of a lookahead DCA code;
- and
- a logic circuit configured to, as part of a lookahead operation, change the lookahead DCA code to each of a plurality of different values, and based on a measurement of the upper clock signal adjusted by the LA DCA, determine a change to the upper DCA code.
An apparatus comprising:
- an upper duty cycle adjustor (DCAU) configured to adjust an upper clock signal based on an upper duty cycle adjustor (DCA) code;
- a lower duty cycle adjustor (DCAL) configured to adjust a lower clock signal based on a lower DCA code;
- an upper lookahead DCA configured to adjust the upper clock signal based on a lookahead DCA code, responsive to an enable signal at an active level;
- a lower lookahead DCA configured to adjust the lower clock signal based on the lookahead DCA code, responsive to the enable signal at an active level;
- an upper duty cycle monitor (DCM) configured to monitor a duty cycle of the upper clock signal responsive to the enable signal at the active level;
- and
- a lower DCM configured to monitor a duty cycle of the lower clock signal responsive to the enable signal at the active level.
An apparatus comprising:
- an upper duty cycle adjustor (DCAU) configured to adjust an upper clock signal based on an upper duty cycle adjustor (DCA) code, wherein the upper clock signal is associated with an upper byte of data;
- a lower duty cycle adjustor (DCAL) configured to adjust a lower clock signal based on a lower DCA code, wherein the lower clock signal is associated with a lower byte of data;
- an upper duty cycle monitor (DCM) configured to monitor the upper clock signal and provide an upper monitor signal with a state based on if the upper clock signal is above or below a target duty cycle;
- a lower DCM configured to monitor the lower clock signal and provide a lower monitor signal with a state based on if the lower clock signal is above or below the target duty cycle;
- a logic circuit configured to, as part of a lookahead operation, vary a value of a lookahead DCA code, latch a value of the lookahead DCA code in a first latch when the upper monitor signal changes states, latch a value of the lookahead DCA code in a second latch when the lower monitor signal changes states, and change the upper DCA code based on the value in the first latch and change the lower DCA code based value in the second latch.
Dependencies are inferred from the claim text.