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US 11,152,920 B2Granted
Voltage starved passgate with IR drop
AssigneeInternational Business Machines Corporation
InventorsMichael Sperling, Akil Khamisi Sutton, Pawel Owczarczyk, Erik English
Life of this patent
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Abstract
Aspects of the invention relate to an apparatus having a transmission gate coupled to a delay element and including a first transistor and a second transistor. A first node is coupled to a first gate of the first transistor, a first current source, and a first resistive element, an opposite end of the first resistive element being coupled to a ground potential. A second node is coupled to a second gate of the second transistor, a second current source, and a second resistive element, an opposite end of the second resistive element being coupled to a power supply.
Claims20
An apparatus comprising:
- a transmission gate coupled to a delay element and comprising a first transistor and a second transistor, the first transistor and the second transistor both having drains shorted together to the delay element and having sources shorted together to an output;
- a first node directly coupled to a first gate of the first transistor which is a PFET, a first current source, and a first resistive element, an opposite end of the first resistive element being coupled to a ground potential;
- and
- a second node directly coupled to a second gate of the second transistor which is an NFET, a second current source, and a second resistive element, an opposite end of the second resistive element being coupled to a power supply, the first node directly coupled to the first gate being different from and not connected to the second node directly coupled to the second gate, the first resistive element being a two-terminal element having no terminal connected to the second node, the second resistive element being another two-terminal element having no terminal connected to the first node;
- wherein a voltage drop up from the ground potential is created at the first node by having the first resistive element coupled to both the ground potential and the first node thereby increasing sensitivity of the first transistor to a voltage droop in the power supply;
- wherein the delay element, the first resistive element, and the second current source are all connected to the ground potential which is a same for all.
3 more elements
A method comprising:
- providing a transmission gate coupled to a delay element, the transmission gate comprising a first transistor and a second transistor, the first transistor and the second transistor both having drains shorted together to the delay element and having sources shorted together to an output;
- coupling a first node directly to a first gate of the first transistor which is a PFET, a first current source, and a first resistive element, an opposite end of the first resistive element being coupled to a ground potential;
- and
- coupling a second node directly to a second gate of the second transistor which is an NFET, a second current source, and a second resistive element, an opposite end of the second resistive element being coupled to a power supply, the first node directly coupled to the first gate being different from and not connected to the second node directly coupled to the second gate, the first resistive element being a two-terminal element having no terminal connected to the second node, the second resistive element being another two-terminal element having no terminal connected to the first node;
- wherein a voltage drop up from the ground potential is created at the first node by having the first resistive element coupled to both the ground potential and the first node thereby increasing sensitivity of the first transistor to a voltage droop in the power supply;
- wherein the delay element, the first resistive element, and the second current source are all connected to the ground potential which is a same for all.
3 more elements
An apparatus comprising:
- a delay element having two transistors coupled together;
- a transmission gate coupled to the delay element and comprising a first transistor and a second transistor, the first transistor and the second transistor both having drains shorted together to the delay element and having sources shorted together to an output;
- a first node directly coupled to a first gate of the first transistor which is a PFET, a first current source, and a first resistive element, an opposite end of the first resistive element being coupled to a ground potential;
- and
- a second node directly coupled to a second gate of the second transistor which is an NFET, a second current source, and a second resistive element, an opposite end of the second resistive element being coupled to a power supply, the first node directly coupled to the first gate being different from and not connected to the second node directly coupled to the second gate, the first resistive element being a two-terminal element having no terminal connected to the second node, the second resistive element being another two-terminal element having no terminal connected to the first node;
- wherein a voltage drop up from the ground potential is created at the first node by having the first resistive element coupled to both the ground potential and the first node thereby increasing sensitivity of the first transistor to a voltage droop in the power supply;
- wherein the delay element, the first resistive element, and the second current source are all connected to the ground potential which is a same for all.
4 more elements
Dependencies are inferred from the claim text.