Multi-level buffers for biasing of radio frequency switches
AssigneeAnalog Devices International Unlimited Company
InventorsMehmet A. Akkaya, Atilim Ergul
Life of this patent
Estimating the term…
Abstract
Multi-level buffers for biasing of radio frequency (RF) switches are provided. An RF switching circuit that includes a field-effect transistor (FET) switch, an impedance, and a multi-level buffer that provides a switch control voltage to a gate of the FET through the impedance is disclosed. The multi-level buffer receives a control signal to turn on or off the FET switch. Additionally, the multi-level buffer is implemented with stacked inverters that operate using different clock signal phases to pulse the switch control voltage in response to a transition of the control signal to thereby shorten a delay in switching the FET switch.
Claims20
A radio frequency (RF) switching circuit comprising:
- a field-effect transistor (FET) switch including a gate;
- an impedance;
- and
- a multi-level buffer having an output terminal connected to the gate of the FET through the impedance, wherein the multi-level buffer comprises a first inverter configured to receive a first clock signal phase and powered by a first supply voltage and a second supply voltage less than the first supply voltage, a second inverter configured to receive a second clock signal phase and powered by the second supply voltage and a third supply voltage less than the second supply voltage, a third inverter configured to receive a third clock signal phase and powered by an output of the first inverter and an output of the second inverter, and a first output switch connected between the output terminal and an output of the third inverter.
A multi-level buffer for driving a transistor gate, the multi-level buffer comprising:
- an output terminal;
- a first inverter configured to receive a first clock signal phase and powered by a first supply voltage and a second supply voltage less than the first supply voltage;
- a second inverter configured to receive a second clock signal phase and powered by the second supply voltage and a third supply voltage less than the second supply voltage;
- a third inverter configured to receive a third clock signal phase and powered by an output of the first inverter and an output of the second inverter;
- and
- a first output switch connected between the output terminal and an output of the third inverter.
A method of radio frequency (RF) switching, the method comprising:
- providing a first clock signal phase to an input of a first inverter that is powered by a first supply voltage and a second supply voltage less than the first supply voltage;
- providing a second clock signal phase to an input of a second inverter that is powered by the second supply voltage and a third supply voltage less than the second supply voltage;
- providing a third clock signal phase to an input of a third inverter that is powered by an output of the first inverter and an output of the second inverter;
- controlling an output voltage at an output terminal using a first output switch connected between the output terminal and an output of the third inverter;
- and
- providing the output voltage to a gate of a field-effect transistor (FET) switch through an impedance.
Dependencies are inferred from the claim text.