US 11,152,902 B2Granted

Semiconductor device and memory system

AssigneeToshiba Memory Corporation

InventorYohei Yasuda

Life of this patent

Estimating the term…

Loading patent…

Abstract

According to one embodiment, there is provided a semiconductor device comprising a first differential amplifier circuit. The first differential amplifier circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The second transistor's gate and drain are connected to the first transistor. The third transistor is diode-connected through the first transistor or diode-connected without passing through the first transistor. Thea fourth transistor is diode-connected through the second transistor or diode-connected without passing through the second transistor. The fifth transistor forms a first current mirror circuit with the third transistor. The sixth transistor is connected to a drain of the first transistor in parallel with the third transistor and forms a second current mirror circuit with the fifth transistor.

Claims20

Dependent claims

A semiconductor device, comprising:

a voltage line;
and
a first differential amplifier circuit, wherein the first differential amplifier circuit includes:
a first transistor;
a second transistor of which a gate is connected to a drain of the first transistor and of which a drain is connected to a gate of the first transistor;
a third transistor of which a source is connected to the voltage line and of which a gate and a drain are electrically connected to each other;
a fourth transistor of which a source is connected to the voltage line and of which a gate and a drain are electrically connected to each other;
a fifth transistor which forms a first current mirror circuit with the third transistor and which is electrically connected to an output node;
a sixth transistor which is connected to the drain of the first transistor in parallel with the third transistor and which forms a second current mirror circuit with the fifth transistor;
and
a seventh transistor which is connected in series to the sixth transistor and which receives a first input signal at a gate.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/022,386Filed 16 Sep 2020 · continuation
Priority: JP 2019-02785119 Feb 2019
Published: US 2020/0266783 A131 Dec 2020
Granted: 19 Oct 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H03F 3/45219
Complementary long tailed pairs having parallel inputs and being supplied in parallel: folded cascode stages
G11C 7/1069
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: i/O lines read…
G11C 7/1078
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data input circuits, e.g. write amplifiers, data…
H03F 3/45183
Using MOSFET transistors as the active amplifying circuit: long tailed pairs

Family

Application16/557,019Parent of this continuation · filed 30 Aug 2019
US 2020/0412310 A1Pre-grant publication · published 31 Dec 2020
US 10,819,295 B2Parent of this continuation
US 2020/0266783 A1Published application
US 11,152,902 B2This patent

From the US filing history. Foreign family members aren’t listed.