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US 11,152,856 B2Granted
Device for limiting a power loss during the sampling of a digital signal
AssigneeWAGO Verwaltungsgesellschaft mbH
InventorsAndreas Patzelt, Christian Voss
Life of this patent
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Abstract
A device for limiting a power loss during the sampling of a digital signal is illustrated. The device comprises a circuit disposed in the signal path of the digital signal, the circuit being configured to reduce a current flow along the signal path in response to a control signal which indicates a sampling pause.
Claims12
A device for limiting a power loss during a sampling of a digital signal, the device comprising:
- a circuit disposed in a signal path of the digital signal, the circuit being configured to reduce a current flow along the signal path in response to a control signal which indicates a sampling pause,
- wherein the device generates the control signal based on at least one current or voltage level of the digital signal,
- wherein the digital signal comprises current or voltage levels of the at least one current or voltage level in a lower current or voltage level range and in an upper current or voltage level range, and
- wherein the device is configured to generate the control signal which indicates a sampling pause when a sampling value is in the upper current or voltage level range.
1 more element
A device for limiting a power loss during a sampling of a digital signal, the device comprising:
- a circuit disposed in a signal path of the digital signal, the circuit being configured to reduce a current flow along the signal path in response to a control signal which indicates a sampling pause,
- wherein the digital signal comprises current/voltage levels in a lower current/voltage level range and in an upper current/voltage level range, and the device is configured to generate the control signal which indicates a sampling pause when a sampling value is in the upper current/voltage level range, and to not generate the control signal which indicates a sampling pause when a sampling value is in the lower current/voltage level range.
A device for limiting a power loss during a sampling of a digital signal, the device comprising:
- a circuit disposed in a signal path of the digital signal, the circuit being configured to reduce a current flow along the signal path in response to a control signal which indicates a sampling pause,
- wherein the device generates the control signal based on at least one current or voltage level of the digital signal, and
- wherein the circuit includes a switching element and a resistor, the control signal opening or closing the switching element, the resistor providing a bypass for the switching element so that the current flow does not cease entirely even during the sampling pause.
Dependencies are inferred from the claim text.