A decoder, comprising a second processor, a second memory storing an instruction executable for the second processor, a second communication interface and a second bus configured to connect the second processor, the second memory and the second communication interface, wherein the second processor is configured to perform, when running the instruction, operations of:
- before decoding processing is performed according to a matrix-based intra prediction (MIP) mode, setting initial right shift parameters corresponding to different sizes and different MIP mode numbers as an uniform offset parameter, wherein the offset parameter indicates a number of right shifting bits of a predicted value;
- and
- when decoding processing is performed according to the MIP mode, performing decoding processing according to the offset parameter.