Low latency compact Clos network controller
AssigneeIntel Corporation
InventorFaisal Khan
Life of this patent
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Abstract
Many network protocols, including certain Ethernet protocols, include specifications for multiplexing using of virtual lanes. Due to skews and/or other uncertainties associated with the process, packets from virtual lanes may arrive at the receiver out of order. The present disclosure discusses implementations of receivers that may use multiplexer based crossbars, such as Clos networks, to reorder the lanes. State-based controllers for the Clos networks and state-based methods to assign routes in are also discussed.
Claims22
An electronic device comprising:
- a Clos network that comprises an ingress stage comprising a plurality of ingress stage crossbars, a middle stage comprising a plurality of middle stage crossbars, and an egress stage comprising a plurality of egress stage crossbars;
- and
- a Clos network controller comprising a state machine configured to, for each de-assigned virtual lane of a plurality of virtual lanes:
- identify a respective ingress stage crossbar associated with a respective virtual lane and a respective egress stage crossbar associated with the respective virtual lane;
- determine a set of available middle stage crossbars for the respective virtual lane based on the respective ingress stage crossbar to the respective egress stage crossbar;
- if the set of available middle stage crossbars is not empty, assign the respective virtual lane to one available middle stage of the set of available middle stage crossbars;
- and
- if the set of available middle stage crossbars is empty, de-assign a previously assigned virtual lane when the set of available middle stage crossbars is empty.
A non-transitory computer readable medium containing program instructions to create, in a programmable logic device, a state machine that comprises a Clos network controller configured to:
- receive a first virtual lane specification comprising a specified input port of a Clos network and a specified output port of the Clos network;
- identify an ingress crossbar of the Clos network associated with the specified input port;
- identify an egress crossbar of the Clos network associated with the specified output port;
- search a set of available middle stage crossbars of the Clos network based on the ingress crossbar and the egress crossbar;
- if the set of available middle stage crossbars is not empty, assign the first virtual lane specification to a first middle stage crossbar of the set of available middle stage crossbars and add the first virtual lane specification to a stack of assigned virtual lanes;
- and
- if the set of available middle stage crossbars is empty, remove a second virtual lane specification from the stack of assigned virtual lanes, and de-assign the second virtual lane specification from a previously assigned second middle stage crossbar.
A method to design routes in a Clos network using a state machine, the method comprising:
- receiving a plurality of input-to-output specifications, wherein each input-to-output specification comprises a respective input port of the Clos network and a respective output port of the Clos network;
- for each input-to-output specification:
- determining a respective ingress crossbar of the Clos network associated with the respective input port;
- determining a respective egress crossbar of the Clos network associated with the respective output port;
- searching a set of available middle stage crossbars of the Clos network that can route the respective ingress crossbar and the respective egress crossbar;
- if the set of available middle stage crossbars is not empty:
- assigning the respective input-to-output specification of the plurality of input-to-output specifications to a first middle stage crossbar of the set of available middle stage crossbars;
- and
- adding the respective input-to-output specification a backtrack stack;
- and
- if the set of available middle stage crossbars is empty:
- removing a second input-to-output specification from the backtrack stack;
- and
- de-assigning the second input-to-output specification from a previously assigned second middle stage crossbar.
Dependencies are inferred from the claim text.