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US 11,146,427 B2Granted
Transition detector and clock data recovery unit including the same
AssigneeSamsung Display Co., Ltd.
InventorJeong Keun Ahn
Life of this patent
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Abstract
A transition detector includes a first integrator configured to provide a first integral signal by integrating a first training pattern signal according to a first compensation clock signal, a second integrator configured to provide a second integral signal by integrating the first training pattern signal according to a second compensation clock signal, and a third integrator configured to provide a third integral signal by integrating the first training pattern signal according to a third compensation clock signal, wherein occurrence of a transition of the first training pattern signal is detected when the first integral signal and the second integral signal are larger than, and the third integral signal is smaller than, a first reference voltage.
Claims20
A transition detector comprising:
- a first integrator configured to provide a first integral signal by integrating a first training pattern signal according to a first compensation clock signal;
- a second integrator configured to provide a second integral signal by integrating the first training pattern signal according to a second compensation clock signal;
- and
- a third integrator configured to provide a third integral signal by integrating the first training pattern signal according to a third compensation clock signal,
- wherein occurrence of a transition of the first training pattern signal is detected in a single case when the first integral signal and the second integral signal are larger than, and the third integral signal is smaller than, a first reference voltage, and
- wherein occurrence of the transition of the first training pattern signal is not detected in other cases.
3 more elements
A transition detector comprising:
- a first integrator configured to provide a first integral signal by integrating a first training pattern signal according to a first compensation clock signal;
- a second integrator configured to provide a second integral signal by integrating the first training pattern signal according to a second compensation clock signal;
- a third integrator configured to provide a third integral signal by integrating the first training pattern signal according to a third compensation clock signal;
- a first comparator configured to output a logic value of 1 when the first integral signal is larger than a first reference voltage, and to output a logic value of 0 when the first integral signal is smaller than the first reference voltage;
- a second comparator configured to output the logic value of 1 when the second integral signal is larger than the first reference voltage, and to output the logic value of 0 when the second integral signal is smaller than the first reference voltage;
- a third comparator configured to output the logic value of 1 when the third integral signal is larger than the first reference voltage, and to output the logic value of 0 when the third integral signal is smaller than the first reference voltage;
- a first NAND gate configured to receive output values of the first comparator and the second comparator;
- and
- a first NOR gate configured to receive output values of the first NAND gate and the third comparator,
- wherein occurrence of a transition of the first training pattern signal is detected when the first integral signal and the second integral signal are larger than, and the third integral signal is smaller than, the first reference voltage,
- wherein the second compensation clock signal has a phase that is further delayed than that of the first compensation clock signal, and
- wherein the third compensation clock signal has a phase that is further delayed than that of the second compensation clock signal.
9 more elements
A clock data recovery unit comprising:
- a first integrator configured to provide a first integral signal by integrating a first training pattern signal according to a first compensation clock signal;
- a second integrator configured to provide a second integral signal by integrating the first training pattern signal according to a second compensation clock signal having a phase further delayed than that of the first compensation clock signal;
- and
- a third integrator configured to provide a third integral signal by integrating the first training pattern signal according to a third compensation clock signal having a phase further delayed than that of the second compensation clock signal,
- wherein the phase of the third compensation clock signal is stored as a first phase in a single case when the first integral signal and the second integral signal are larger than, and the third integral signal is smaller than, a first reference voltage, and
- wherein the phase of the third compensation clock signal is not stored as the first phase in other cases.
3 more elements
Dependencies are inferred from the claim text.