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US 11,146,411 B2Granted
Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD
AssigneeSamsung Electronics Co., Ltd.
InventorSompong Paul Olarig
Life of this patent
Estimating the term…
Abstract
A chassis front-end is disclosed. The chassis front-end may include a switchboard including an Ethernet switch, a Baseboard Management Controller, and a mid-plane connector. The chassis front-end may also include a mid-plane including at least one storage device connector and a speed logic to inform at least one storage device of an Ethernet speed of the chassis front-end. The Ethernet speeds may vary.
Claims20
A chassis front-end, comprising:
- a switchboard including an Ethernet switch, a processor, a Baseboard Management Controller (BMC), and a mid-plane connector to connect to a mid-plane;
- and
- a mid-plane including at least one storage device connector to connect to at least one storage device and a speed logic to inform the at least one storage device of a speed of the Ethernet switch, wherein the Ethernet switch is one of a first Ethernet switch supporting a first Ethernet speed and a second Ethernet switch supporting a second Ethernet speed.
A method, comprising:
- receiving an Ethernet speed of an Ethernet switch at a Baseboard Management Controller (BMC) on a switchboard from a chassis;
- and
- informing, by the BMC, a storage device in the chassis connected to a chassis front-end of the Ethernet speed of the Ethernet switch, the chassis front-end including the switchboard and a mid-plane, wherein the Ethernet switch is one of a first Ethernet switch supporting a first Ethernet speed and a second Ethernet switch supporting a second Ethernet speed.
A storage device, comprising:
- data storage to store data;
- a controller to manage reading and writing data to the data storage;
- a storage device connector to connect the storage device to a mid-plane in a chassis, the storage device connector including a plurality of pins;
- a bit file storage to store at least two Ethernet speed bit files;
- and
- a mapping logic to map the data from the data storage to the plurality of pins on the storage device connector responsive to one of the at least two Ethernet speed bit files.
3 more elements
Dependencies are inferred from the claim text.