Signal receiving device and method of recovering clock and calibration of the device

A signal receiving device comprising:

• a first variable gain amplifier configured to amplify a signal level of a first differential signal, which is a differential signal between a first input signal and a second input signal among first to third input signals based on a first gain control signal, the first to third input signals each having a different signal level relative to other ones of the first to third input signals in each of a plurality of unit intervals;
• a second variable gain amplifier configured to amplify the signal level of the first differential signal based on a second gain control signal;
• a first level detector configured to output a first comparison signal in response to an output of the first variable gain amplifier being greater than a first reference signal level;
• a second level detector configured to output a second comparison signal, in response to an output of the second variable gain amplifier being greater than a second reference signal level;
• a clock data recovering device configured to recover a clock signal embedded in the first to third input signals based on the first comparison signal and the second comparison signal to generate a recovery clock signal;
• and
• a calibration device configured to adjust the first gain control signal based on the first comparison signal.

A signal receiving device comprising:

• a first level detector configured to output a first comparison signal of a plurality of comparison signals based on a first differential signal, a first reference signal level and a second reference signal level different from the first reference signal level, the first differential signal being a differential signal between a first input signal and a second input signal among the first input signal, the second input signal and a third input signal, the first to third input signals each having a different signal level relative to other ones of the first to third input signals in each of a plurality of unit intervals;
• a second level detector configured to output a second comparison signal of the plurality of comparison signals based on a second differential signal, the first reference signal level and the second reference signal level, the second differential signal being a differential signal between the second input signal and the third input signal among the first to third input signals;
• a third level detector configured to output a third comparison signal of the plurality of comparison signals based on a third differential signal, the first reference signal level and the second reference signal level, the third differential signal being a differential signal between the third input signal and the first input signal;
• an SR latch configured to output wire state information of the first to third input signals, based on the plurality of comparison signals;
• and
• a plurality of OR gates configured to recover a clock signal embedded in the first to third input signals based on the plurality of comparison signals to generate a recovery clock signal.