Decoding method, memory storage device, and memory controlling circuit unit

A memory storage device, comprising:

• a connection interface unit configured to couple to a host system;
• a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells;
• and
• a memory controlling circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module,
• wherein the memory controlling circuit unit is configured to receive a read command sequence, wherein the read command sequence is for reading a plurality of bits from the memory cells,
• the memory controlling circuit unit is further configured to obtain a first count value of a first value and a second count value of a second value in the bits through a counter,
• the memory controlling circuit unit is further configured to adjust a decoding parameter corresponding to the bits to a specific decoding parameter according to the first count value and the second count value, comprising:
• reducing the decoding parameter corresponding to the first value or increasing the decoding parameter corresponding to the second value in response to a difference between the first count value and the second count value being greater than 0, and
• increasing the decoding parameter corresponding to the first value or reducing the decoding parameter corresponding to the second value in response to the difference between the first count value and the second count value being less than 0, and
• the memory controlling circuit unit is further configured to perform a decoding operation according to the specific decoding parameter, wherein the adjusted decoding parameter affects a probability that the bits are considered as an error bit in the decoding operation.

A memory controlling circuit unit for controlling a memory storage device comprising a rewritable non-volatile memory module, the memory controlling circuit unit comprising:

• a host interface, configured to couple to a host system,
• a memory interface, configured to couple to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells;
• and
• a memory management circuit, coupled to the host interface and the memory interface;
• wherein the memory controlling circuit unit is configured to receive a read command sequence, wherein the read command sequence is for reading a plurality of bits from the memory cells,
• the memory controlling circuit unit is further configured to obtain a first count value of a first value and a second count value of a second value in the bits through a counter,
• the memory controlling circuit unit is further configured to adjust a decoding parameter corresponding to the bits to a specific decoding parameter according to the first count value and the second count value, comprising:
• reducing the decoding parameter corresponding to the first value or increasing the decoding parameter corresponding to the second value in response to a difference between the first count value and the second count value being greater than 0, and
• increasing the decoding parameter corresponding to the first value or reducing the decoding parameter corresponding to the second value in response to the difference between the first count value and the second count value being less than 0, and
• the memory controlling circuit unit is further configured to perform a decoding operation according to the specific decoding parameter, wherein the adjusted decoding parameter affects a probability that the bits are considered as an error bit in the decoding operation.