Polar coder with logical three-dimensional memory, communicaton unit, integrated circuit and method therefor

A communication unit comprising a polar coder circuit comprising:

• one or more datapaths;
• at least one logical three-dimensional, 3D, memory block coupled to the one or more datapaths and comprising two or more random access memories, RAMs, of the at least one logical 3D memory block as a first dimension, wherein the two or more RAMs comprise(s) a width of one or more element(s) as a second dimension and a depth of one or more address(es) as a third dimension and wherein the first dimension or the second dimension has a size of two to the power of a number of stages in a datapath of the one or more datapaths;
• and
• a controller coupled to the at least one logical 3D memory block and configured to direct the one or more datapaths to process bits that are read from the at least one logical 3D memory block across at least one of the first dimension and the second dimension, and configured to direct the one or more datapaths to write processed bits to the at least one logical 3D memory block across at least one of the first dimension and the second dimension;
• and at least one of:
• wherein each of a group of processed number of bits provided at an output of the one or more datapaths is written in a single write operation to the at least one logical 3D memory block;
• wherein each of a group of processed number of bits required at an input of the datapath of the one or more datapaths is seamlessly obtained in a single read operation from the at least one logical 3D memory block.

An integrated circuit for a wireless communication unit, the integrated circuit comprising a polar coder circuit comprising:

• one or more datapaths;
• at least one logical three-dimensional, 3D, memory block coupled to the one or more datapaths and comprising two or more random access memories, RAMs, of the at least one logical 3D memory block as a first dimension, wherein the two or more RAMs comprise(s) a width of one or more element(s) as a second dimension and a depth of one or more address(es) as a third dimension and wherein the first dimension or the second dimension has a size of two to the power of a number of stages in a datapath of the one or more datapaths;
• and
• a controller coupled to the at least one logical 3D memory block and configured to direct the one or more datapaths to process bits that are read from the at least one logical 3D memory block across at least one of the first dimension and the second dimension, and configured to direct the one or more datapaths to write processed bits to the at least one logical 3D memory block across at least one of the first dimension and the second dimension;
• and at least one of:
• wherein each of a group comprising a number of processed bits provided at an output of the one or more datapaths is written in a single write operation to the at least one logical 3D memory block;
• wherein each of a group comprising a number of processed bits required at an input of the datapath of the one or more datapaths is seamlessly obtained in a single read operation from the at least one logical 3D memory block.

A method of polar coding in a polar coder circuit that comprises one or more datapaths and at least one logical three-dimensional, 3D, memory block coupled to the one or more datapaths, the method comprising:

• apportioning the at least one logical 3D memory block as a first dimension that is two or more random access memories, RAMs, of the at least one logical 3D memory block;
• a second dimension that is a width of one or more element(s) of each of the two or more RAMs;
• and a third dimension that is a depth of one or more address(es) of each of the one or more RAMs;
• wherein the first dimension or the second dimension has a size of two to the power of a number of stages in a datapath of the one or more datapaths;
• directing the one or more datapaths to process bits that are read from the at least one logical 3D memory block across at least one of the first dimension and the second dimension;
• and
• directing the one or more datapaths to write processed bits to the at least one logical 3D memory block across at least one of the first dimension and the second dimension;
• and at least one of:
• wherein each of a group comprising a number of processed bits provided at an output of the one or more datapaths is written in a single write operation to the at least one logical 3D memory block;
• wherein each of a group comprising a number of processed bits required at an input of the datapath of the one or more datapaths is seamlessly obtained in a single read operation from the at least one logical 3D memory block.

A non-transitory tangible computer program product comprising executable code stored therein for polar coding, wherein the code is operable for, when executed at a polar coder that comprises one or more datapaths and at least one logical three-dimensional, 3D, memory block coupled to the one or more datapaths:

• apportioning the at least one logical 3D memory block as a first dimension that is two or more random access memories, RAMs, of the at least one logical 3D memory block;
• a second dimension that is a width of one or more element(s) of each of the two or more RAMs;
• and
• a third dimension that is a depth of one or more address(es) of each of the one or more RAMs;
• wherein the first dimension or the second dimension has a size of two to the power of a number of stages in a datapath of the one or more datapaths;
• and
• directing the one or more datapaths to process bits that are read from the at least one logical 3D memory block across at least one of the first dimension and the second dimension;
• and
• directing the one or more datapaths to write processed bits to the at least one logical 3D memory block across at least one of the first dimension and the second dimension;
• and at least one of:
• wherein each of a group comprising a number of processed bits provided at an output of the one or more datapaths is written in a single write operation to the at least one logical 3D memory block;
• wherein each of a group comprising a number of processed bits required at an input of the datapath of the one or more datapaths is seamlessly obtained in a single read operation from the at least one logical 3D memory block.