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US 11,146,289 B2Granted
Techniques to use intrinsic information for a bit-flipping error correction control decoder
AssigneeIntel Corporation
InventorsAman Bhatia, Zion S. Kwok, Justin Kang, Poovaiah M. Palangappa, Santhosh K. Vanaparthy
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Abstract
Examples include techniques to use intrinsic information when implementing a bit-flipping algorithm. An error correction control (ECC) decoder uses the intrinsic information to decode a low density parity count (LDPC) codeword. The intrinsic information including bits of a copy of a received LDPC codeword are compared to bits for variable nodes during an iteration of the bit-flipping algorithm to aid a determination as whether one or more bits for the variable nodes are to be flipped.
Claims20
An error correction control (ECC) decoder comprising:
- a first buffer;
- a second buffer;
- and
- circuitry to:
- receive a low density parity check (LDPC) codeword;
- store bits of the LDPC codeword in the first buffer for use of each bit of the LDPC codeword as a separate variable node for implementing a bit-flipping algorithm;
- store information that includes the bits of the LDPC codeword in the second buffer;
- determine whether one or more check nodes coupled with the separate variable nodes according to a Tanner graph are unsatisfied based on separate parity check equations for the one or more check nodes calculated during an iteration of the bit-flipping algorithm;
- compare the bits of the LDPC codeword stored in the second buffer to bits for the separate variable nodes;
- adjust a value associated with one or more criteria for flipping a bit included in individual bits of the separate variable nodes based on whether the bit matches a respective binary value for a corresponding bit of the LDPC codeword stored in the second buffer;
- cause the bit to flip based on the adjusted value equaling or exceeding a bit-flipping threshold value;
- and
- decode the LDPC codeword with the flipped bit based on all check nodes coupled with the separate variable nodes being satisfied following the flipping of the bit.
10 more elements
A method comprising:
- receiving a low density parity check (LDPC) codeword;
- storing bits of the LDPC codeword in a first buffer of a bit-flipping error correction control (ECC) decoder for use of each bit of the LDPC codeword as a separate variable node by the bit-flipping ECC decoder;
- storing information that includes the bits of the LDPC codeword in a second buffer of the bit-flipping ECC decoder;
- determining whether one or more check nodes coupled with the separate variable nodes according to a Tanner graph are unsatisfied based on separate parity check equations for the one or more check nodes calculated during an iteration of a bit-flipping algorithm;
- comparing the bits of the LDPC codeword stored in the second buffer to bits for the separate variable nodes;
- adjusting a value associated with one or more criteria for flipping a bit included in individual bits of the separate variable nodes based on whether the bit matches a respective binary value for a corresponding bit of the LDPC codeword stored in the second buffer;
- causing the bit to flip based on the adjusted value equaling or exceeding a bit-flipping threshold value;
- and
- decoding the LDPC codeword with the flipped bit based on all check nodes coupled with the separate variable nodes being satisfied following the flipping of the bit.
6 more elements
An apparatus comprising:
- at least one memory device;
- and
- a controller that includes an error correction control (ECC) decoder, the ECC decoder to include:
- a first buffer;
- a second buffer;
- and
- circuitry to:
- receive a low density parity check (LDPC) codeword from the at least one memory device;
- store bits of the LDPC codeword in the first buffer for use of each bit of the LDPC codeword as a separate variable node for implementing a bit-flipping algorithm;
- store information that includes the bits of the LDPC codeword in the second buffer;
- determine whether one or more check nodes coupled with the separate variable nodes according to a Tanner graph are unsatisfied based on separate parity check equations for the one or more check nodes calculated during an iteration of the bit-flipping algorithm;
- compare the bits of the LDPC codeword stored in the second buffer to bits for the separate variable nodes;
- adjust a value associated with one or more criteria for flipping a bit included in individual bits of the separate variable nodes based on whether the bit matches a respective binary value for a corresponding bit of the LDPC codeword stored in the second buffer;
- cause the bit to flip based on the adjusted value equaling or exceeding a bit-flipping threshold value;
- and
- decode the LDPC codeword with the flipped bit based on all check nodes coupled with the separate variable nodes being satisfied following the flipping of the bit.
13 more elements
Dependencies are inferred from the claim text.