Calibration of residual errors using least-mean-squares (LMS) and stochastic-gradient methods for an analog-to-digital converter (ADC) with a pre-calibrated lookup table

A self-calibrating mixed-signal converter comprising:

• an array of digital-analog elements, each for converting a binary bit to an analog signal;
• a comparator that compares two analog inputs to generate a compare result;
• a Least-Significant-Bit (LSB) digital-analog element in the array of digital-analog elements, the LSB digital-analog element having a smallest effect on the two analog inputs, the LSB digital-analog element having an ideal radix of one;
• wherein other digital-analog elements in the array of digital-analog elements each have an ideal radix that is a function of a ratio of a design size of a digital-analog element to the design size of the LSB digital-analog element;
• wherein the array of digital-analog elements comprise at least five digital-analog elements with different design sizes and having at least five different values of the ideal radix;
• wherein the array of digital-analog elements is connected to at least one of the two analog inputs to the comparator wherein each of the at least five digital-analog elements with different design sizes cause at least five different values of an effect on at least one of the two analog inputs to the comparator;
• wherein manufactured sizes of the digital-analog elements differ from the design sizes by an error amount;
• a Successive-Approximation Register (SAR) that applies a SAR search sequence of binary bits to a portion of the array of digital-analog elements having an ideal radix less than a target ideal radix of a target digital-analog element in the array of digital-analog elements;
• wherein bits are set or cleared in the SAR during the SAR search sequence in response to the compare result from the comparator to generate a final SAR value when the SAR search sequence is completed;
• a summer for summing the ideal radixes for digital-analog elements having a corresponding bit set in the final SAR value to generate a target measured radix;
• a first Look-Up Table (LUT) that stores the target measured radix from the summer for the target digital-analog element, the first LUT also storing the ideal radixes for the portion of the array of digital-analog elements having the ideal radix that is less than the target ideal radix of the target digital-analog element, and stores target measured radixes for other digital-analog elements having an ideal radix greater than the target ideal radix;
• a code complementor that receives the binary bits from the SAR and generates a complement code for the binary bits, the complement code including a sign bit that indicates when the complement code is positive and when the complement code is negative;
• a positive LUT having positive entries copied from the first LUT and adjusted for first non-linearity errors determined by a secondary calibration routine;
• a negative LUT having negative entries copied from the first LUT and adjusted for second non-linearity errors determined by the secondary calibration routine;
• a first summer for summing the positive entries in the positive LUT for digital-analog elements having a corresponding bit set in the complement code, the first summer also adding a first offset to generate a corrected output when the sign bit indicates that the complement code is positive;
• and
• a second summer for summing the negative entries in the negative LUT for digital-analog elements having a corresponding bit cleared to zero in the complement code, the second summer also adding a second offset and negating a sum to generate the corrected output when the sign bit indicates that the complement code is negative;
• whereby the corrected output is generated from the positive LUT when the sign bit of the complement code is positive, and the corrected output is generated from the negative LUT when the sign bit of the complement code is negative.

An Analog-Digital converter comprising:

• an array of digital-analog elements, each for converting a binary bit to an analog signal;
• a comparator that compares an analog comparator input coupled to the array to generate a compare result;
• a Successive-Approximation Register (SAR) that applies a SAR search sequence of binary bits to the array of digital-analog elements;
• wherein the binary bits are set or cleared in the SAR during the SAR search sequence in response to the compare result from the comparator to generate a final SAR value when the SAR search sequence is completed;
• a code complementor that generates a complement code from the binary bits from the SAR, the complement code having a sign bit;
• a positive Look-Up Table (LUT) that stores positive entries that correspond to a plurality of calibrated sizes of the digital-analog elements in the array, wherein the positive entries are adjusted by first error values;
• a negative LUT that stores negative entries that correspond to the plurality of calibrated sizes of the digital-analog elements in the array, wherein the negative entries are adjusted by second error values;
• and
• a summer that generates a corrected code by summing the positive entries having a corresponding bit set in the complement code and adding a first offset and dividing by a sum of all the positive entries when the sign bit indicates a positive complement code;
• wherein the summer further generates the corrected code by summing the negative entries having a corresponding bit cleared in the complement code and adding a second offset and dividing by a sum of all the negative entries when the sign bit indicates a negative complement code.