Methods and apparatus for a successive approximation register analog-to-digital converter
AssigneeSemiconductor Components Industries, LLC
InventorsRajashekar Benjaram, Maheedhar Suryadevara
Life of this patent
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Abstract
Various embodiments of the present technology may provide methods and apparatus for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC may provide a first digital calibration circuit configured to correct systemic mismatch and a second digital calibration circuit configured to correct random mismatch. Together, the first and second digital calibration circuits resolve missing codes in the SAR ADC output.
Claims20
A calibration circuit configured to connect to a set of analog-to-digital converters (ADCs) and receive an ADC output code from each ADC, comprising:
- a first calibration sub-circuit configured to perform a first calibration that compensates for a first error type that is shared among each ADC output code and comprising:
- a logic circuit configured to initiate the first calibration in response to a start signal;
- a first control circuit in communication with the logic circuit and configured to generate a subtracted code according to a switching point code and the ADC output code;
- a counter in communication with the logic circuit and configured to determine a code count based on the subtracted code;
- a missing code generator in communication with the logic circuit and configured to determine a missing code count based on the code count and an average code count;
- and
- a weight generator in communication with the logic circuit and configured to assign a weight to the missing code count and correct the ADC output code according to the assigned weight;
- and
- a second calibration sub-circuit connected to the first calibration sub-circuit and configured to perform a second calibration that compensates for a second error type that occurs among different ADC output codes.
A method for calibrating ADC output codes from a set of analog-to-digital converters (ADCs), comprising:
- performing a first calibration on each ADC output code to compensate for a first error type, comprising:
- generating a subtracted code according to a switching point code and the ADC output code;
- determining a code count based on the subtracted code;
- determining a missing_code_count based on the code count and an average code count;
- and
- assigning a weight to the missing_code_count and correct the ADC output code according to the assigned weight;
- performing a second calibration on each ADC output code to compensate for a second error type that occurs among different ADC output codes;
- and
- generating a corrected ADC output code according to the first and second calibrations.
A system, comprising:
- a set of analog-to-digital converters (ADCs) wherein each ADC generates an ADC output code;
- and
- a calibration circuit connected to the set of ADCs and configured to receive the ADC output code from each ADC, wherein the calibration circuit comprises:
- a first calibration sub-circuit configured to perform a first calibration on each ADC output code to compensate for a first error type, the first calibration comprising:
- generating a subtracted code according to a switching point code and the ADC output code;
- determining a code count based on the subtracted code;
- determining a missing_code_count based on the code count and an average code count;
- and
- assign a weight to the missing_code_count and correct the ADC output code according to the assigned weight;
- and
- a second calibration sub-circuit connected to the first calibration sub-circuit and configured to perform a second calibration to compensate for a second error type;
- wherein the calibration circuit generates a corrected ADC output code for each ADC output code according to the first and second calibrations.
Dependencies are inferred from the claim text.