Frequency locked loop with fast reaction time

A method comprising:

• generating a frequency signal using a frequency locked loop by:
• generating a frequency signal (F) using a digitally controlled oscillator (102);
• generating, by a frequency counter and sequencer circuit (310), an estimate (f_EST) of the frequency of the frequency signal (F) by counting periods of the frequency signal (F) during a counting phase having a start and an end timed by corresponding transitions of a reference clock signal (CLK_REF), the frequency counter and sequencer circuit (310) also having a computing phase during which periods of the frequency signal are not counted;
• generating, by a subtracter (112), an error signal (f_ERR) by determining the difference between the estimated frequency (f_EST) and a target frequency (f_TAR);
• generating, by a controller (314), a digital control signal (C_FREQ) for controlling the digitally controlled oscillator (102) based on the error signal, wherein the controller (314) is clocked by a further clock signal (CLK), different from the reference clock signal, the further clock signal having a variable frequency;
• generating, and providing to the frequency counter and sequencer circuit (310), by the controller (314), a trigger signal (AUTO_CLEAR) for triggering, after resynchronization of the trigger signal with the reference clock signal (CLK_REF), the end of the computing phase;
• and
• synchronizing, by a resynchronization circuit (312) of the frequency counter and sequencer circuit (310), the trigger signal (AUTO_CLEAR) with the reference clock signal (CLK_REF).

A frequency locked loop comprising:

• a digitally controlled oscillator (102) configured to generate a frequency signal (F);
• a frequency counter and sequencer circuit (310) configured to generate an estimate (f_EST) of the frequency of the frequency signal (F) by counting periods of the frequency signal (F) during a counting phase having a start and an end timed by corresponding transitions of a reference clock signal (CLK_REF), the frequency counter and sequencer circuit (310) being further configured to have a computing phase during which periods of the frequency signal are not counted, the frequency counter and sequencer circuit (310) further comprising a resynchronization circuit (312) configured to synchronize the trigger signal (AUTO_CLEAR) with the reference clock signal (CLK_REF), the resynchronization circuit (312) comprising first and second flip-flops (402, 404) each clocked by the reference clock signal (CLK_REF), the first flip-flop (402) receiving the trigger signal (AUTO_CLEAR), and the second flip-flop (404) outputting a resynchronized trigger signal (END_COMPUTE), and
• a controller (314) configured to generate a digital control signal (C_FREQ) for controlling the digitally controlled oscillator (102) based on the estimated frequency (f_EST), wherein the controller (314) is clocked by a further clock signal (CLK) having a variable frequency, and the controller (314) is configured to generate a trigger signal (AUTO_CLEAR) for triggering, after resynchronization of the trigger signal with the reference clock signal (CLK_REF), the end of the computing phase.