Equalizer control device, receiving device, and control method for receiving device
AssigneeKioxia Corporation
InventorMikio Shiraishi
Life of this patent
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Abstract
An equalizer control device includes a first circuit configured to, upon receipt of a data signal that has been equalized by a continuous time linear equalizer (CTLE) circuit, output a first signal related to a first number of times a waveform of the data signal crosses a threshold value or differential signals of the data signal cross each other. A second circuit is configured to count the first number during a particular time period based on the output first signal, and select one of equalization parameters to be set to the CTLE circuit based on the counted first number.
Claims20
An equalizer control device, comprising:
- a first circuit configured to, upon receipt of a data signal that has been equalized by a continuous time linear equalizer (CTLE) circuit, output a first signal related to a first number of times a waveform of the data signal crosses a threshold value or differential signals of the data signal cross each other;
- and
- a second circuit configured to count the first number during a particular time period based on the output first signal and select one of equalization parameters to be set for the CTLE circuit based on the counted first number.
A receiving device, comprising:
- a continuous time linear equalizer (CTLE) circuit configured to equalize a data signal;
- a first circuit configured to, upon receipt of the equalized data signal from the CTLE circuit, output a first signal related to a first number of times a waveform of the equalized data signal crosses a threshold value or differential signals of the equalized data signal cross each other;
- a second circuit configured to count the first number during a particular time period based on the output first signal, and select one of equalization parameters to be set for the CTLE circuit based on the counted first number;
- a third circuit configured to output a first clock signal;
- and
- a fourth circuit configured to recover a second clock signal from the data signal based on the first clock signal from the third circuit and the first signal from the first circuit.
A control method, comprising:
- receiving a data signal that has been equalized by a continuous time linear equalizer (CTLE) circuit;
- outputting a first signal related to a first number of times a waveform of the data signal crosses a threshold value or differential signals of the data signal cross each other;
- counting the first number during a particular time period based on the output first signal;
- and
- selecting one of equalization parameters to be set for the CTLE circuit based on the counted first number.
Dependencies are inferred from the claim text.