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US 11,146,272 B2Granted
Comparator
AssigneeSK hynix Inc.
InventorChang Hyun Kim
Life of this patent
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Abstract
A semiconductor device includes a selection signal generation circuit configured to generate a selection signal by comparing a first input signal and a second input signal. The semiconductor device also includes a comparison signal generation circuit configured to output a comparison signal by selecting one of the first input signal and the second input signal based on the selection signal.
Claims19
A semiconductor device comprising:
- a selection signal generation circuit configured to generate a selection signal by comparing a first input signal and a second input signal;
- and
- a comparison signal generation circuit configured to output a comparison signal by selecting one of the first input signal and the second input signal responsive to the selection signal, the comparison signal generation circuit comprising a plurality of serially-connected code selection circuits, each code selection circuit having:
- first and second input signal ports, a selection signal port and an output port from which the comparison signal is output responsive to a signal provided to the selection signal port;
- wherein a logic level of the comparison signal output from each serially-connected code selection circuit is set responsive to a comparison of a first signal input to the first signal input port to a second input to the second signal input port;
- wherein the comparison signal has a first logic level when the first signal input to the first signal input port is equal to or smaller than the second signal input to the second signal input port;
- wherein the comparison signal has a second logic level when the first signal input to the first signal input port is greater than the second signal input to the second signal port;
- and,
- wherein each of the first input signal and the second input signal comprises more bits than the comparison signal.
6 more elements
A semiconductor device comprising:
- a selection signal generation circuit configured to generate an (N−1){circumflex over ( )}th bit of a selection signal which has a first logic level, when an N{circumflex over ( )}th bit of a first input signal is different from an N{circumflex over ( )}th bit of a second input signal;
- and
- a comparison signal generation circuit configured to receive first and second input signals and configured to output the N{circumflex over ( )}th bit of the first input signal as a comparison signal when the (N−1){circumflex over ( )}th bit of the selection signal has the first logic level, wherein N is a natural number of 2 or more, the comparison signal generation circuit comprising a plurality of serially-connected code selection circuits, each code selection circuit having:
- first and second input signal ports, a selection signal port and an output port from which the comparison signal is output responsive to the value of a signal provided to the selection signal port;
- wherein the comparison signal has a first logic level when the first input signal is set to be equal to or smaller than the second input signal,
- wherein the comparison signal has a second logic level when the first input signal is set to be larger than the second input signal, and
- wherein each of the first input signal and the second input signal comprises more bits than the comparison signal.
4 more elements
A semiconductor device comprising:
- a selection signal generation circuit configured to generate an (N−1){circumflex over ( )}th bit of a selection signal which has a first logic level, when an N{circumflex over ( )}th bit of a first input signal is different from an N{circumflex over ( )}th bit of a second input signal;
- and
- a comparison signal generation circuit configured to receive first and second input signals and which is configured to output a comparison signal by inverting and buffering the N{circumflex over ( )}th bit of the second input signal when the (N−1){circumflex over ( )}th bit of the selection signal has the first logic level, wherein N is a natural number of 2 or more, the comparison signal generation circuit comprising a plurality of serially-connected code selection circuits, each code selection circuit having:
- first and second input signal ports, a selection signal port and an output port from which the comparison signal is output responsive to the value of a signal provided to the selection signal port;
- wherein the comparison signal has a first logic level when the first input signal is set to be equal to or smaller than the second input signal,
- wherein the comparison signal has a second logic level when the first input signal is set to be larger than the second input signal, and
- wherein each of the first input signal and the second input signal comprises more bits than the comparison signal.
4 more elements
Dependencies are inferred from the claim text.