Controlled current manipulation for regenerative charging of gate capacitance

A circuit for regenerative gate charging, the circuit comprising:

• an inductor having a first terminal and a second terminal, the second terminal being configured to be coupled to a gate node of a field effect transistor (FET);
• a bridged inductor driver circuit being configured to be coupled to the first terminal of the inductor and the second terminal of the inductor, the bridged inductor driver circuit comprising a plurality of switches;
• an output control circuit coupled to the bridged inductor driver circuit;
• a sense circuit configured to be coupled to the gate node;
• a timing control circuit coupled to the output control circuit and the sense circuit;
• and
• a plurality of adjustable delay circuits coupled to the timing control circuit;
• wherein:
• the output control circuit holds one or more of the plurality of switches in an ON state for a first time period of a first switching cycle using first output control signals, the first time period being in accordance with a first switch timing profile, and the first switch timing profile being determined prior to the first switching cycle;
• the output control circuit holds all of the plurality of switches in an OFF state for a second time period of the first switching cycle, the second time period being in accordance with the first switch timing profile and beginning after an expiration of the first time period;
• the sense circuit samples one or more first voltages of the gate node during the second time period;
• the timing control circuit uses the one or more sampled first voltages to generate a second switch timing profile for a second switching cycle;
• the output control circuit holds one or more of the plurality of switches in the ON state for a third time period of the second switching cycle using second output control signals, the third time period being in accordance with the second switch timing profile;
• the output control circuit holds all of the plurality of switches in the OFF state for a fourth time period of the second switching cycle, the fourth time period being in accordance with the second switch timing profile;
• the first output control signals are generated during the first switching cycle using the plurality of adjustable delay circuits;
• the first time period and the second time period are determined by the plurality of adjustable delay circuits;
• respective first adjustable delay values of the plurality of adjustable delay circuits are in accordance with the first switch timing profile during the first switching cycle;
• the second output control signals are generated during the second switching cycle using the plurality of adjustable delay circuits;
• the third time period and the fourth time period are determined by the plurality of adjustable delay circuits;
• and
• respective second adjustable delay values of the plurality of adjustable delay circuits are in accordance with the second switch timing profile during the second switching cycle.