Process controlled output driver staggering
AssigneeTexas Instruments Incorporated
InventorAmar Kanteti
Life of this patent
Estimating the term…
Abstract
An output buffer includes a first group of stagger FETs coupled in parallel between a power lead and an output signal lead and a second group of stagger FETs coupled in parallel between the output signal lead and a ground lead. Each stagger FET has a gate coupled to a respective base resistor and a respective adjustable resistor. A first group of bypass FETs and a second group of bypass FETs are each coupled across the terminals of a respective adjustable resistor and the gates of the bypass FETs are coupled to either a first process-sensing signal lead or a second process-sensing signal lead.
Claims20
An electronic device comprising:
- a first group of stagger field effect transistors (FETs) coupled in parallel between an output domain power lead and an output signal lead, a gate of each of the first group of stagger FETs being coupled to a respective first base resistor and a respective first adjustable resistor, the respective first base resistors and the respective first adjustable resistors being coupled in series and coupled to a first gate control signal lead;
- a first group of bypass FETs, each of the first group of bypass FETs being coupled across the terminals of the respective first adjustable resistor, a gate of each of the first group of bypass FETs being coupled to a first process-sensing signal lead;
- a second group of stagger FETs coupled in parallel between the output signal lead and a ground lead, a gate of each of the second group of stagger FETs being coupled to a respective second base resistor and a respective second adjustable resistor, the respective second base resistors and the respective second adjustable resistors being coupled in series and coupled to a second gate control signal lead;
- and
- a second group of bypass FETs, each of the second group of bypass FETs being coupled across the terminals of the respective second adjustable resistor, a gate of each of the second group of bypass FETs being coupled to a second process-sensing signal lead.
A method of performing staggering in an output driver having a first gate control signal lead, a second gate control signal lead, and an output signal lead, the method comprising:
- providing a first process-sensing circuit having a first process-sensing input lead and a first process-sensing output lead, the first process-sensing input lead being coupled to the first gate control signal lead;
- providing a second process-sensing circuit having a second process-sensing input lead and a second process-sensing output lead, the second process-sensing input lead being coupled to the second gate control signal lead;
- and
- during staggering in the output driver,
- selectively bypassing a first group of adjustable stagger resistors based on a first pulse provided on the first process-sensing output lead,
- selectively bypassing a second group of adjustable stagger resistors based on a second pulse provided on the second process-sensing output lead, and
- selectively boosting an output signal on the output signal lead based on the first pulse and the second pulse.
Dependencies are inferred from the claim text.