Receiving circuit to process low-voltage signal with hysteresis

A receiving circuit comprising:

• a hysteresis detector configured to receive an input signal, to output a detection signal having a first threshold voltage and a second threshold voltage, and to use a first power supply voltage and a reference voltage;
• and
• a level shifter configured to receive the detection signal, to convert a voltage level of the detection signal so as to be output as an output signal, to provide a feedback signal to the hysteresis detector, and to use a second power supply voltage greater than the first power supply voltage,
• wherein the hysteresis detector includes:
• a first PMOS transistor connected between a node of receiving the first power supply voltage and a first node and configured to operate in response to the input signal;
• a second PMOS transistor connected between the first node and a second node and configured to operate in response to the input signal;
• a first NMOS transistor connected between the second node and a third node and configured to operate in response to the input signal;
• a second NMOS transistor connected between the third node and a ground node and configured to operate in response to the input signal;
• a third PMOS transistor connected between the first node and a node of receiving the reference voltage and configured to operate in response to the feedback signal;
• a third NMOS transistor connected between the third node and the node of receiving the reference voltage and configured to operate in response to the feedback signal;
• a first inverter configured to receive the detection signal and to invert the detection signal so as to be output as an inverted detection signal;
• and
• a second inverter configured to receive the inverted detection signal and to invert the inverted detection signal so as to be output as an second detection signal, and
• wherein the level shifter includes:
• a fourth PMOS transistor connected between a node of receiving the second power supply voltage and a fourth node and configured to operate in response to a signal of a fifth node;
• a fifth PMOS transistor connected between the node of receiving the second power supply voltage and the fifth node and configured to operate in response to a signal of the fourth node;
• a fourth NMOS transistor connected between the fourth node and the ground node and configured to operate in response to the inverted detection signal;
• and
• a fifth NMOS transistor connected between the fifth node and the ground node and configured to operate in response to the second detection signal.