Logic and flip-flop circuit timing margins controlled based on scan-pattern transition processing
AssigneeNXP B.V.
InventorJan-Peter Schat
Life of this patent
Estimating the term…
Abstract
One specific example involves an integrated circuit that has application logic circuitry which includes flip-flop circuits susceptible to degradations of setup and hold times relative to specified minimum setup and hold times for signals to be processed by the respective flip-flop circuits. In a method carried out by the integrated circuit, timing-based logic states of the flip-flop circuits are controlled, based on at least one transition-scan pattern processed by the flip-flop circuits as part of the application logic circuitry; and respective logic states are set for those flip-flops, which due to degradations of the actual setup and hold times do not satisfy anymore the originally specified minimum setup and hold times.
Claims20
In an integrated circuit having application logic circuitry which includes flip-flop circuits susceptible to degradations of setup and hold times relative to specified minimum setup and hold times for signals to be processed by the respective flip-flop circuits, a method carried out by the integrated circuit and comprising:
- controlling timing-based logic states of the flip-flop circuits based on at least one transition-scan pattern processed by the flip-flop circuits as part of the application logic circuitry;
- and
- setting respective logic states of the flip-flop circuits in instances where due to degradations, actual setup and hold times do not satisfy criteria for the specified minimum setup and hold times.
An apparatus comprising:
- application logic circuitry including flip-flop circuits susceptible to degradations of setup and hold times relative to specified minimum setup and hold times for signals to be processed by the respective flip-flop circuits;
- and
- control circuitry to control timing-based logic states of the flip-flop circuits based on at least one transition-scan pattern processed by the flip-flop circuits as part of the application logic circuitry, and to set logic states of the flip-flop circuits in instances where due to degradations, actual setup and hold times do not satisfy criteria for the specified minimum setup and hold times.
Dependencies are inferred from the claim text.