Pad protection in an integrated circuit

In an integrated circuit (IC) having a signal pad configured to communicate external to the IC, an output buffer coupled to provide signals to the signal pad and an input buffer coupled to receive signals from the signal pad, a method comprising:

• determining that a voltage on the signal pad is both greater than a predetermined low threshold voltage and lower than a predetermined high threshold voltage for a continuous amount of time greater than a predetermined period of time, wherein the predetermined low threshold voltage corresponds to a threshold below which a voltage corresponds to a logic level zero and the predetermined high threshold voltage corresponds to a threshold above which a voltage corresponds to a logic level one;
• in response to determining that the voltage on the signal pad is both greater than the predetermined low threshold voltage and lower than the predetermined high threshold voltage for the continuous amount of time greater than the predetermined period of time, disabling the input buffer such that no signal from the signal pad is transmitted through the input buffer;
• and
• after disabling the input buffer, when the voltage on the signal pad either goes higher than the predetermined high threshold voltage or goes lower than the predetermined low threshold voltage, reenabling the input buffer.

A integrated circuit comprising:

• a signal pad;
• an output buffer having an output coupled to the signal pad and having an enable input;
• an input buffer having an input coupled to the signal pad and having an enable input;
• a counter which is enabled to start counting down a predetermined count value when a voltage on the signal pad is both higher than a predetermined low threshold voltage and lower than a predetermined high threshold voltage, wherein the predetermined low threshold voltage corresponds to a threshold below which a voltage corresponds to a logic level zero and the predetermined high threshold voltage corresponds to a threshold above which a voltage corresponds to a logic level one;
• and
• a gating circuit, coupled to the counter and the enable inputs of the input and output buffers, configured to, in response to the counter expiring, disable the input buffer and the output buffer.

A integrated circuit comprising:

• a reset signal pad coupled to receive a reset signal from an external source;
• an output buffer having an output coupled to the reset signal pad;
• an input buffer having an enable input coupled to receive an enable signal and a data input coupled to the reset signal pad;
• a counter having:
• a counter enable input wherein the counter is enabled to start counting down a predetermined count value when a voltage on the signal pad is both higher than a predetermined low threshold voltage and lower than a predetermined high threshold voltage, wherein the predetermined low threshold voltage corresponds to a threshold below which a voltage corresponds to a logic level zero and the predetermined high threshold voltage corresponds to a threshold above which a voltage corresponds to a logic level one, and
• a counter expired output configured to provide a gating value, wherein when the counter expires, the gating value forces the enable input to disable the input buffer until the counter is reset and while the counter is not expired, the gating value allows the input buffer to be selectively enabled and disabled.