Resistive random access memory cells integrated with vertical field effect transistor

A vertical field effect transistor, comprising:

• a channel region extending from a doped source on a substrate;
• a metal gate material disposed on and around the channel region between a first spacer and a second spacer;
• a first interlevel dielectric layer adjacent to the second spacer;
• a top source/drain region comprising an epitaxial region above the channel region, the epitaxial region being separated from the channel region by the second spacer, the epitaxial region comprising two opposing protruding regions of triangular shape extending outwardly from the channel region;
• a dielectric cap above a top surface of the epitaxial region;
• an oxide layer conformally deposited on a top surface of the first interlevel dielectric layer, a top surface of the second spacer, a top surface of each protruding region of the epitaxial region and on sidewalls of the dielectric cap;
• a top electrode layer conformally deposited on the oxide layer;
• and
• and a metal fill deposited above the top electrode layer for forming a resistive random access memory element on each side of the epitaxial region, each protruding region of the epitaxial region of the top source/drain region acting as a bottom electrode for the resistive random access memory element on each side of the epitaxial region.