Bottom electrode for semiconductor memory device

An interconnect structure in a memory device comprising:

• an insulator layer on a substrate, the insulator layer having a recess therein;
• a microstud comprised of a conductive material;
• a bottom pedestal on a top surface of the microstud, wherein a material used for the bottom pedestal has a lower electrochemical voltage than a material used for the microstud;
• a top pedestal on a top surface of the bottom pedestal;
• a conductive layer on a top surface of the top pedestal;
• and
• a conical structure, wherein the conical structure is comprised of at least the conductive layer and a top portion of the top pedestal and wherein the top surface of the top pedestal is planarized.

A method for fabricating a structure for an integrated circuit device comprising:

• providing a conductive microstud on a substrate, the microstud being formed in a recess of an insulator layer formed on the substrate;
• forming a bottom pedestal on a top surface of the microstud, wherein a material used for the bottom pedestal has a lower electrochemical voltage than a material used for the microstud;
• forming a top pedestal on a top surface of the bottom pedestal;
• planarizing the top surface of at least one of the bottom pedestal and top pedestal;
• forming a conductive layer on a top surface of the top pedestal;
• and
• forming a conical structure, wherein the conical structure is comprised of at least the conductive layer and a top portion of the top pedestal;
• wherein the top pedestal is comprised of TiN, the bottom pedestal is comprised of TaN and the microstud is comprised of Cu.